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b=AgWD21JKqoSiLfs8qY5F5YIBdip4idq8ktpTKDDypTlVGF5e1WbBaPpyupBK3kHEh6 quNucrRTKk+nKIIYsyYS47LMxqkkMgPqSIh5qywCszc9w0rWJmB7qlyUgNeaKdNF/0sR u++LPyk1KwxkMatQxc0hIHGvnt/pv9QRb8r273D0CRZpO5IQCUnKFsVu65/AqPPDmk8p BcgEioWO5PbgQIRcdT0ph1oOA0wOhG3Q8HCp7cwASfPFVGIG9W/oDtl5q/zfgYm/4NFc N+ZR/g+WIrWhE0sP2hBBlinDyz26dzewxRw4D6SBMIbwceha2HX/mbaANMvxaf63jCF3 RjhA== X-Forwarded-Encrypted: i=1; AJvYcCV1cEPhk6qfFiTgK3Dq7oqVJElGU6VFNh5DaFvR4yZNQP7E9m92aeYbvzYCCIVqfZKtOhC+8pPaewpJpPC41xIfDHgS X-Gm-Message-State: AOJu0YyScLgSu/3yeBj+0eUPIUBTHbgtnmx+gm276HD6M8zB0YaQuiw7 DJUVpy6aWTWLW+Ri5aMCOdw27+IALvbeGZDrkxoOV9cvTAeNl7Ghq7pR4mmjNK++RieSzFyACY7 4Pzbyxg== X-Google-Smtp-Source: AGHT+IEclZ07ukoLzf1pYkJmmMQ+HHGVZo5A5QV38BQbp8xRkfjknzqxOFAU5OGM6vN1ghMRe70pBmZRHJTv X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a05:6a00:6f46:b0:70d:1e28:1c33 with SMTP id d2e1a72fcca58-7105d68fecfmr34795b3a.1.1722488455721; Wed, 31 Jul 2024 22:00:55 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:59:05 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-57-mizhang@google.com> Subject: [RFC PATCH v3 56/58] KVM: x86/pmu/svm: Wire up PMU filtering functionality for passthrough PMU From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Manali Shukla With the Passthrough PMU enabled, the PERF_CTLx MSRs (event selectors) are always intercepted and the event filter checking can be directly done inside amd_pmu_set_msr(). Add a check to allow writing to event selector for GP counters if and only if the event is allowed in filter. Signed-off-by: Manali Shukla Signed-off-by: Mingwei Zhang --- arch/x86/kvm/svm/pmu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 86818da66bbe..9f3e910ee453 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -166,6 +166,15 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (data != pmc->eventsel) { pmc->eventsel = data; if (is_passthrough_pmu_enabled(vcpu)) { + if (!check_pmu_event_filter(pmc)) { + /* + * When guest request an invalid event, + * stop the counter by clearing the + * event selector MSR. + */ + pmc->eventsel_hw = 0; + return 0; + } data &= ~AMD64_EVENTSEL_HOSTONLY; pmc->eventsel_hw = data | AMD64_EVENTSEL_GUESTONLY; } else {