diff mbox series

[kvm-unit-tests,v2,7/7] riscv: mmu: Ensure order of PTE update and sfence

Message ID 20240812134451.112498-16-andrew.jones@linux.dev (mailing list archive)
State New, archived
Headers show
Series riscv: 32-bit should use phys_addr_t | expand

Commit Message

Andrew Jones Aug. 12, 2024, 1:44 p.m. UTC 
Use WRITE_ONCE to ensure the compiler won't order the page table
write after the TLB flush.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
---
 lib/riscv/mmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/lib/riscv/mmu.c b/lib/riscv/mmu.c
index ce49e67be84b..577c66aa77ba 100644
--- a/lib/riscv/mmu.c
+++ b/lib/riscv/mmu.c
@@ -64,7 +64,8 @@  static pteval_t *__install_page(pgd_t *pgtable, phys_addr_t paddr,
 	assert(!(ppn & ~PTE_PPN));
 
 	ptep = get_pte(pgtable, vaddr);
-	*ptep = __pte(pte | pgprot_val(prot) | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+	pte |= pgprot_val(prot) | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY;
+	WRITE_ONCE(*ptep, __pte(pte));
 
 	if (flush)
 		local_flush_tlb_page(vaddr);