From patchwork Tue Aug 13 14:47:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762163 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F1701A0706; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; cv=none; b=r5tF4yWKUOqUAtH9j0jeld8SY/97gg5wA+ppkNsN1aFEa49NFlc4GnUKbZwN5dQmYIJZJdOwkDMVK35id6cG3r+hYYlxtKBu1dxEzHLSYxhr6vC0kW9Czfhpl3z2hQBWNvZ/PXk6sKkvqCc72DpM3uDsFZI1Bu9L9CfX2FrANzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; c=relaxed/simple; bh=KQvPl9jkOYcV8P9wWE6qdftXypsGkKyrUThzcFU4ltI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lCZJS1kr9+SONZgyA+46b647y4Xba+IYA31zCm7I5JFbuFKFaTV4Lt2s46h0NJpVb0ubGmJPbkORezWgpmokjtTpe9oASlIUEOy94bPDgresENwnH5IlHEnLxDMcs0JqjJPMW2vQwjL4rI0oWVUYXVg3MZPM0LN9b2QNcuooTe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FNgtxxsT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FNgtxxsT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEDC7C4AF09; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=KQvPl9jkOYcV8P9wWE6qdftXypsGkKyrUThzcFU4ltI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FNgtxxsTxMK/KISWsCyudIeBOfKdkd1O0ce2uB0wiWghdziy21ij6bUK6nSCvu0jv 78caEUd945rYdLXm+7BFotvBenAupm+DyU/zkHr45ty1miJcjfncOerun9PfI63iCf vMq5uOtVXjGKAN2jtQuiJeQoVo7PeHxL7ZQdbGyHvsWRkgp3uh8jd4i2ZKPoWLtnxx LBNJYVb2RkHafsAh01BQ9KVMfjUnzDPAc3o3FJJHQSC/GXRRA5OLx0FFHpkUdSYWwB 1aDlaqdXop7lM2ngI511ADeZbIfHvhk468hiIe71T1i2dXqW/px8NwC/tRR1MHueO6 VIRqxtRR8gWyA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-Tg; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 09/10] KVM: arm64: Handle PIR{,E0}_EL2 traps Date: Tue, 13 Aug 2024 15:47:37 +0100 Message-Id: <20240813144738.2048302-10-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the FEAT_S1PIE EL2 registers the sysreg descriptor array so that they can be handled as a trap. Access to these registers is conditionned on ID_AA64MMFR3_EL1.S1PIE being advertised. Similarly to other other changes, PIRE0_EL2 is guaranteed to trap thanks to the D22677 update to the architecture.. Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly --- arch/arm64/kvm/sys_regs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 52250db3c122..a5f604e24e05 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -346,6 +346,18 @@ static bool access_rw(struct kvm_vcpu *vcpu, return true; } +static bool check_s1pie_access_rw(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) { + kvm_inject_undefined(vcpu); + return false; + } + + return access_rw(vcpu, p, r); +} + /* * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). */ @@ -2827,6 +2839,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), EL2_REG(MAIR_EL2, access_rw, reset_val, 0), + EL2_REG(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0), + EL2_REG(PIR_EL2, check_s1pie_access_rw, reset_val, 0), EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), EL2_REG(VBAR_EL2, access_rw, reset_val, 0),