diff mbox series

[3/9] i386/cpu: Add support for bits in CPUID.7_2.EDX

Message ID 20240814075431.339209-4-xiaoyao.li@intel.com (mailing list archive)
State New, archived
Headers show
Series Misc patches for x86 CPUID | expand

Commit Message

Xiaoyao Li Aug. 14, 2024, 7:54 a.m. UTC 
KVM started to report the support of bit 0-5 since commit eefe5e668209
("Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace")

Allow them to be exposed to guest in QEMU.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e60d9dd58b60..03376ccf3e75 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1148,8 +1148,8 @@  FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
     [FEAT_7_2_EDX] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
-            NULL, NULL, NULL, NULL,
-            NULL, "mcdt-no", NULL, NULL,
+            "psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
+            "bhi-ctrl", "mcdt-no", NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,