From patchwork Tue Sep 3 15:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13788962 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6FC818B466; Tue, 3 Sep 2024 15:38:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725377922; cv=none; b=YvLZxYW3m5rmGXHFWeXU3oR2WOyLIayh+JkXocOCLN2xwVTZOCt8lGTOnk769r8PHJKjNi74TjzZu1yScQ7WFgkUqEtNhbJ9hP8pLPrAeTRPNI3MnzNrrJVdu+7ZvmrLXPK+BUOxbHppPkJbEWJz+iIkf9Sc4GRFyGaOTagScyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725377922; c=relaxed/simple; bh=3hq9V1F6GHZbXXg8saZsb1o9QP9sp/62P1fdCT+OhbU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nmXVJSCMit9UwEb2FpskkEAh41mJP1FDCgRRHv6cNFDfjtGWcrXgVm8CT8VHK6EsAgb5lo499GlLEzQSxKSCDeZbLod/7R+uocaWes5hNoTnUfOVaZk2CMotzR9RtlFF7tT3Ml7GoEqlcBZaUZ06sIi87Ke3TjqogoINybEs0/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JxPfzbqH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JxPfzbqH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8E23CC4CED2; Tue, 3 Sep 2024 15:38:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725377922; bh=3hq9V1F6GHZbXXg8saZsb1o9QP9sp/62P1fdCT+OhbU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JxPfzbqHES9DH1wZqMzPAEcH0u8OU9/Cdbdes01TEMCtSasBSCA46HDLydDaQpTN+ dmrG4uw/s+dZLpmPzFq7GORZo50EWicxA7URRbDzab0yXPXdHPqccNSxKC9R5UrNLq LDoG8yzGplJWpYNocv0XXvb6n/w5vn+7OgLnBvYRaJUkH2hzw70l9rZJ+oKqlhh0qt 08uqtxAerJq+fV9nblquvkAzjYEJOovskyZC8qbPcPTAsFAybZtYQUq8XYbHktDCtz HDhWyy82WOJEtTQOi/gWAgvFiCUGAO42ceyq5njiw2hVULZtqOWS8mJclSTn84SJbD mXxkLxWUVkCag== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1slVc8-009Hr9-Lh; Tue, 03 Sep 2024 16:38:40 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei , Mark Brown Subject: [PATCH v2 10/16] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Date: Tue, 3 Sep 2024 16:38:28 +0100 Message-Id: <20240903153834.1909472-11-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240903153834.1909472-1-maz@kernel.org> References: <20240903153834.1909472-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we solely expose S1PIE and TCRX (we currently don't support anything else). Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a6bc20c238bf..7f4f69351e89 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1608,6 +1608,9 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, case SYS_ID_AA64MMFR2_EL1: val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; break; + case SYS_ID_AA64MMFR3_EL1: + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1PIE; + break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -2470,7 +2473,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64MMFR2_EL1_IDS | ID_AA64MMFR2_EL1_NV | ID_AA64MMFR2_EL1_CCIDX)), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | + ID_AA64MMFR3_EL1_S1PIE)), ID_SANITISED(ID_AA64MMFR4_EL1), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6),