From patchwork Sun Sep 8 12:59:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13795444 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D77CF161924 for ; Sun, 8 Sep 2024 12:43:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799430; cv=none; b=MM86kiXNKU3CoW3J9JtgAo4t81rGNziMNt+KJJKtf8o4Z5qbimZuVnvBjfAZGuN7UKzoVmEu+wC14yKtKGV2mhCt+OmVgXqI/9vucXFS9ZifI0YD+RaIes5YSwLmx/5hhvvOkTOlrhbj16haepXOKllqqNl2GI+7vsW/vRpp6uA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799430; c=relaxed/simple; bh=fLVPMHMbGbgr75ZVdN2bSb3F9f9e89UFzrkPV2gAPm8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BziVSeXLQjS6q8qNE9r6VLYdtPoUaNyyJjMFvanhbeWM4Y4qFfSDwrK8n6K3vAAmMC9dzINvp1gD0Ln8pkGB+P2GSQbEP0hfGMuhKvBEdhClh9DWeBExYTTldNF1XHEIRxI3n5EZgPQ0IP36KSABaQgK8i/83zk7fKE1f9CnHL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Gg9JIZbF; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Gg9JIZbF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725799429; x=1757335429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fLVPMHMbGbgr75ZVdN2bSb3F9f9e89UFzrkPV2gAPm8=; b=Gg9JIZbFVQayo1tRZuoBpAopMOR1rAqJqFHNhb6FN2eXaNf3a/Aatqrf ubvJK3TxJ+I5VCZyArbq8n29qgjXoVI2HaSERxISPXcCwyVa5rEjWpB3u AdY63wyIrzbqP4ixW+TU8TVZpzUqR8zdlzvQ0Ziu+7zDccRsyOsGT7sCo Y57jh5sVBIwukZ+zheO48j+qUeKOQzCYMGC/yPPWh9dR+YHjekdigrN7A V6FMQcqQls8XlEtgAPP/Ys+ZiIbUovhhO2jbRW9xHMpxD07imzYTSwXPp 8D7vEUtqjjVRz0PuqBIbpVN1nHaN0+DUMRXsNbEzCWEz+3Sbvf/tVvnCD A==; X-CSE-ConnectionGUID: RK/CjlZNS9aHv1jDIqRvLw== X-CSE-MsgGUID: OWuK56XVRC6NoErfF6BZ7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11189"; a="28238184" X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="28238184" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2024 05:43:49 -0700 X-CSE-ConnectionGUID: diEO//HXSLaEty83F5KDtQ== X-CSE-MsgGUID: 5rBdS2Y5RB28Y9qO0dYIpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="97196586" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 08 Sep 2024 05:43:43 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v2 4/7] hw/core: Check smp cache topology support for machine Date: Sun, 8 Sep 2024 20:59:17 +0800 Message-Id: <20240908125920.1160236-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240908125920.1160236-1-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- Changes since Patch v1: * Dropped machine_check_smp_cache_support() and did the check when -machine parses smp-cache in machine_parse_smp_cache(). Changes since RFC v2: * Split as a separate commit to just include compatibility checking and topology checking. * Allow setting "default" topology level even though the cache isn't supported by machine. (Daniel) --- hw/core/machine-smp.c | 78 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 ++ 2 files changed, 81 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b517c3471d1a..9a281946762f 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,47 @@ void machine_parse_smp_config(MachineState *ms, } } +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) || + (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) || + (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SmpCache *smp_cache, + CacheLevelAndType cache1, + CacheLevelAndType cache2) +{ + if (smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + smp_cache->props[cache1].topology > smp_cache->props[cache2].topology) { + return true; + } + return false; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc = MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); @@ -293,6 +330,47 @@ bool machine_parse_smp_cache(MachineState *ms, } } + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props = &ms->smp_cache.props[i]; + + /* + * Allow setting "default" topology level even though the cache + * isn't supported by machine. + */ + if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } + + if (smp_cache_topo_cmp(&ms->smp_cache, + CACHE_LEVEL_AND_TYPE_L1D, + CACHE_LEVEL_AND_TYPE_L2) || + smp_cache_topo_cmp(&ms->smp_cache, + CACHE_LEVEL_AND_TYPE_L1I, + CACHE_LEVEL_AND_TYPE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cache"); + return false; + } + + if (smp_cache_topo_cmp(&ms->smp_cache, + CACHE_LEVEL_AND_TYPE_L2, + CACHE_LEVEL_AND_TYPE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cache"); + return false; + } + return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index 64439dc7da2c..6c3cdfa15f50 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -150,6 +150,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache topologies (l1d, l1i, l2 and l3) are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -159,6 +161,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; /**