From patchwork Sun Sep 8 12:59:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13795445 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65B8416089A for ; Sun, 8 Sep 2024 12:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799435; cv=none; b=l+gdCeEV3ClZHnpqEzScAURJkrhC3yOpzsfBmn3Cp2cUQOwxpBFjB320kyIwsEC54jnzl8yo6PEMXKUddddPb1PM+oX9qSQ5U5xnmB4DIRPYTDdT86HZACAIyVy8VOVDD43ygElxfkz50xH3gsL5qqRK8ythyKokyNyrqcTyzE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799435; c=relaxed/simple; bh=mnsZhLOSkIt6OGn4y2rRLWIdhUwNFa/JuPtwCtNqbec=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XIEJX8vZ8OSSHr7Rl3LF95hVpQ4p3JLlMohQSyMEjbqy0MWbFIMcf4ST0YIADQRuTaJZEkTiz5qM6rDnECwoRpUBxWCdGi8m+76owooM1/ZKyaK0QcJtVTGWi71CzlfUs8MAdohPbwt4Yf2otk3pNla/+XNaQRuZbIGgps4jkCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TX3miRD0; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TX3miRD0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725799435; x=1757335435; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mnsZhLOSkIt6OGn4y2rRLWIdhUwNFa/JuPtwCtNqbec=; b=TX3miRD0EjWbGavj2yLEiWeDeS9osOod2VTnb3kRdHeDeYtbo1G6fau+ 356qfxb4cJpCdC8fXa+FmYayG48w4UiJtDDOynTXV6kHCAMWY00LvcrzN 6Nc0uiS+xDwo8A6rV3sYZhbgjMeXSt8CPx9pmuP54HI39/920UL7xiyGE Rjcr1XJdZH56RxWMinDreuJJ9v01gD/c4Qat2oA1SN+wVf8fySYnMjDHm rg7d90As19SGrL5PE6QOJSob7AuQsCt7eSlLvkqZoQN8bZnDBh/TZEN9x 5I1jNBy7kgui4Ur+lR7FjXDjjqPMixFV/0Nha8CW5q06YdQPkfhFCj/vR Q==; X-CSE-ConnectionGUID: sB0n+edWTiKFjvzzaKuJGQ== X-CSE-MsgGUID: XIKAWW7KTF6k0CIXPbwjgw== X-IronPort-AV: E=McAfee;i="6700,10204,11189"; a="28238215" X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="28238215" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2024 05:43:54 -0700 X-CSE-ConnectionGUID: bvTZQcDaRguVcTIRDYQTng== X-CSE-MsgGUID: KH+c+HSBRdiHXCVmCm6NkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="97196618" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 08 Sep 2024 05:43:48 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v2 5/7] i386/cpu: Support thread and module level cache topology Date: Sun, 8 Sep 2024 20:59:18 +0800 Message-Id: <20240908125920.1160236-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240908125920.1160236-1-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e3a81bc64922..e9f755000356 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); }