diff mbox series

[v3,03/24] arm64: Add encoding for PIRE0_EL2

Message ID	20240911135151.401193-4-maz@kernel.org (mailing list archive)
State	New, archived
Headers	show Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07FA01A264B; Wed, 11 Sep 2024 13:51:58 +0000 (UTC) From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com>, Joey Gouly <joey.gouly@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Mark Brown <broonie@kernel.org> Subject: [PATCH v3 03/24] arm64: Add encoding for PIRE0_EL2 Date: Wed, 11 Sep 2024 14:51:30 +0100 Message-Id: <20240911135151.401193-4-maz@kernel.org> In-Reply-To: <20240911135151.401193-1-maz@kernel.org> References: <20240911135151.401193-1-maz@kernel.org> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	KVM: arm64: Add EL2 support to FEAT_S1PIE \| expand [v3,00/24] KVM: arm64: Add EL2 support to FEAT_S1PIE [v3,01/24] arm64: Drop SKL0/SKL1 from TCR2_EL2 [v3,02/24] arm64: Remove VNCR definition for PIRE0_EL2 [v3,03/24] arm64: Add encoding for PIRE0_EL2 [v3,04/24] KVM: arm64: nv: Add missing EL2->EL1 mappings in get_el2_to_el1_mapping() [v3,05/24] KVM: arm64: nv: Handle CNTHCTL_EL2 specially [v3,06/24] KVM: arm64: nv: Save/Restore vEL2 sysregs [v3,07/24] KVM: arm64: Correctly access TCR2_EL1, PIR_EL1, PIRE0_EL1 with VHE [v3,08/24] KVM: arm64: Extend masking facility to arbitrary registers [v3,09/24] arm64: Define ID_AA64MMFR1_EL1.HAFDBS advertising FEAT_HAFT [v3,10/24] KVM: arm64: Add TCR2_EL2 to the sysreg arrays [v3,11/24] KVM: arm64: Sanitise TCR2_EL2 [v3,12/24] KVM: arm64: Add save/restore for TCR2_EL2 [v3,13/24] KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays [v3,14/24] KVM: arm64: Add save/restore for PIR{,E0}_EL2 [v3,15/24] KVM: arm64: Handle PIR{,E0}_EL2 traps [v3,16/24] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 [v3,17/24] KVM: arm64: Add AT fast-path support for S1PIE [v3,18/24] KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts [v3,19/24] KVM: arm64: Disable hierarchical permissions when S1PIE is enabled [v3,20/24] KVM: arm64: Implement AT S1PIE support [v3,21/24] KVM: arm64: Define helper for EL2 registers with custom visibility [v3,22/24] KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests [v3,23/24] KVM: arm64: Hide S1PIE registers from userspace when disabled for guests [v3,24/24] KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF

Commit Message

Marc Zyngier Sept. 11, 2024, 1:51 p.m. UTC

PIRE0_EL2 is the equivalent of PIRE0_EL1 for the EL2&0 translation
regime, and it is sorely missing from the sysreg file.

Add the sucker.

Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/tools/sysreg | 4 ++++
 1 file changed, 4 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 27c71fe3952f1..d80859565547e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2852,6 +2852,10 @@  Sysreg	PIRE0_EL12	3	5	10	2	2
 Fields	PIRx_ELx
 EndSysreg
 
+Sysreg	PIRE0_EL2	3	4	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
 Sysreg	PIR_EL1		3	0	10	2	3
 Fields	PIRx_ELx
 EndSysreg