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Szmigiero" , Harsh Prateek Bora , Kevin Wolf , Paolo Bonzini , Jesper Devantier , Hyman Huang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-s390x@nongnu.org, Laurent Vivier , qemu-riscv@nongnu.org, "Richard W.M. Jones" , Liu Zhiwei , Aurelien Jarno , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Marcel Apfelbaum , kvm@vger.kernel.org, Christian Borntraeger , Akihiko Odaki , Daniel Henrique Barboza , Hanna Reitz , Ani Sinha , qemu-ppc@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Alistair Francis , Bin Meng , "Michael S. Tsirkin" , Helge Deller , Peter Xu , Daniel Henrique Barboza , Dmitry Fleytman , Nina Schoetterl-Glausch , Yanan Wang , qemu-arm@nongnu.org, Igor Mammedov , Jean-Christophe Dubois , Eric Farman , Sriram Yagnaraman , qemu-block@nongnu.org, Stefan Berger , Joel Stanley , Eduardo Habkost , David Gibson , Fam Zheng , Weiwei Li , Markus Armbruster , Pierrick Bouvier Subject: [PATCH v2 34/48] target/riscv: remove break after g_assert_not_reached() Date: Thu, 12 Sep 2024 00:39:07 -0700 Message-Id: <20240912073921.453203-35-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240912073921.453203-1-pierrick.bouvier@linaro.org> References: <20240912073921.453203-1-pierrick.bouvier@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier --- target/riscv/monitor.c | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 2 -- 2 files changed, 3 deletions(-) diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f5b1ffe6c3e..100005ea4e9 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -184,7 +184,6 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) break; default: g_assert_not_reached(); - break; } /* calculate virtual address bits */ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3a3896ba06c..f8928c44a8b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3172,7 +3172,6 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base, break; default: g_assert_not_reached(); - break; } } @@ -3257,7 +3256,6 @@ static void store_element(TCGv_i64 val, TCGv_ptr base, break; default: g_assert_not_reached(); - break; } }