Message ID | 20240919044641.386068-23-pierrick.bouvier@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71944bc279csm7478601b3a.188.2024.09.18.21.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 21:47:29 -0700 (PDT) From: Pierrick Bouvier <pierrick.bouvier@linaro.org> To: qemu-devel@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Hyman Huang <yong.huang@smartx.com>, Halil Pasic <pasic@linux.ibm.com>, kvm@vger.kernel.org, Bin Meng <bmeng.cn@gmail.com>, Peter Xu <peterx@redhat.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, David Gibson <david@gibson.dropbear.id.au>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, qemu-s390x@nongnu.org, Dmitry Fleytman <dmitry.fleytman@gmail.com>, Hanna Reitz <hreitz@redhat.com>, Klaus Jensen <its@irrelevant.dk>, Corey Minyard <minyard@acm.org>, Laurent Vivier <laurent@vivier.eu>, WANG Xuerui <git@xen0n.name>, Thomas Huth <thuth@redhat.com>, Rob Herring <robh@kernel.org>, Eduardo Habkost <eduardo@habkost.net>, Nicholas Piggin <npiggin@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, Harsh Prateek Bora <harshpb@linux.ibm.com>, "Maciej S. Szmigiero" <maciej.szmigiero@oracle.com>, Ani Sinha <anisinha@redhat.com>, Stefan Berger <stefanb@linux.vnet.ibm.com>, Fam Zheng <fam@euphon.net>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <philmd@linaro.org>, Keith Busch <kbusch@kernel.org>, Jean-Christophe Dubois <jcd@tribudubois.net>, qemu-riscv@nongnu.org, Igor Mammedov <imammedo@redhat.com>, Akihiko Odaki <akihiko.odaki@daynix.com>, Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>, Jason Wang <jasowang@redhat.com>, Eric Farman <farman@linux.ibm.com>, "Richard W.M. Jones" <rjones@redhat.com>, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>, Nina Schoetterl-Glausch <nsg@linux.ibm.com>, Aurelien Jarno <aurelien@aurel32.net>, Markus Armbruster <armbru@redhat.com>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Fabiano Rosas <farosas@suse.de>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, qemu-arm@nongnu.org, Christian Borntraeger <borntraeger@linux.ibm.com>, qemu-ppc@nongnu.org, Zhao Liu <zhao1.liu@intel.com>, Daniel Henrique Barboza <danielhb413@gmail.com>, qemu-block@nongnu.org, Joel Stanley <joel@jms.id.au>, Weiwei Li <liwei1518@gmail.com>, Kevin Wolf <kwolf@redhat.com>, Helge Deller <deller@gmx.de>, Yanan Wang <wangyanan55@huawei.com>, Michael Rolnik <mrolnik@gmail.com>, Jesper Devantier <foss@defmacro.it>, Marcelo Tosatti <mtosatti@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, Pierrick Bouvier <pierrick.bouvier@linaro.org> Subject: [PATCH v3 22/34] target/riscv: remove break after g_assert_not_reached() Date: Wed, 18 Sep 2024 21:46:29 -0700 Message-Id: <20240919044641.386068-23-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240919044641.386068-1-pierrick.bouvier@linaro.org> References: <20240919044641.386068-1-pierrick.bouvier@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: <kvm.vger.kernel.org> List-Subscribe: <mailto:kvm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:kvm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
Series |
Use g_assert_not_reached instead of (g_)assert(0,false)
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expand
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diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f5b1ffe6c3e..100005ea4e9 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -184,7 +184,6 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) break; default: g_assert_not_reached(); - break; } /* calculate virtual address bits */ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3a3896ba06c..f8928c44a8b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3172,7 +3172,6 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base, break; default: g_assert_not_reached(); - break; } } @@ -3257,7 +3256,6 @@ static void store_element(TCGv_i64 val, TCGv_ptr base, break; default: g_assert_not_reached(); - break; } }