| Message ID | 20240920-dev-maxh-svukte-rebase-v1-2-7864a88a62bd@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: add Svukte extension | expand |
On Fri, Sep 20, 2024 at 03:39:04PM +0800, Max Hsu wrote: >Svukte extension introduce senvcfg.UKTE, hstatus.HUKTE. > >This patch add CSR bit definition, and detects if Svukte ISA extension >is available, cpufeature will set the correspond bit field so the >svukte-qualified memory accesses are protected in a manner that is >timing-independent of the faulting virtual address. > >Since hstatus.HU is not enabled by linux, enabling hstatus.HUKTE will >not be affective. > >This patch depends on patch "riscv: Per-thread envcfg CSR support" [1] > >Link: https://lore.kernel.org/linux-riscv/20240814081126.956287-1-samuel.holland@sifive.com/ [1] > >Reviewed-by: Samuel Holland <samuel.holland@sifive.com> >Signed-off-by: Max Hsu <max.hsu@sifive.com> >--- > arch/riscv/include/asm/csr.h | 2 ++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 4 ++++ > 3 files changed, 7 insertions(+) Reviewed-by: Deepak Gupta <debug@rivosinc.com>
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04e090ff22a11e35be9bc24712f1a8..62b50667d539c50a0bfdadd1c6ab06cda948f6a8 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -122,6 +122,7 @@ #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif +#define HSTATUS_HUKTE _AC(0x01000000, UL) #define HSTATUS_VTSR _AC(0x00400000, UL) #define HSTATUS_VTW _AC(0x00200000, UL) #define HSTATUS_VTVM _AC(0x00100000, UL) @@ -195,6 +196,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_UKTE (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5a0bd27fd11a6d3d3b573c19ebaeb89d23dd8535..87f88a3b3f967b27b50ed071eace631c50d07dc7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -92,6 +92,7 @@ #define RISCV_ISA_EXT_ZCF 83 #define RISCV_ISA_EXT_ZCMOP 84 #define RISCV_ISA_EXT_ZAWRS 85 +#define RISCV_ISA_EXT_SVUKTE 86 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3b9735cb19a8a155b2e6710223ffd0992b8133e..891225a605547b312ab81d81f76f9bbba6c1b658 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -384,6 +384,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg_exts), }; const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); @@ -925,6 +926,9 @@ void __init riscv_user_isa_enable(void) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n"); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) + current->thread.envcfg |= ENVCFG_UKTE; } #ifdef CONFIG_RISCV_ALTERNATIVE