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Fri, 20 Sep 2024 15:35:04 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 11/13] vfio/cxl: introduce VFIO CXL device cap Date: Fri, 20 Sep 2024 15:34:44 -0700 Message-ID: <20240920223446.1908673-12-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|DS7PR12MB5719:EE_ X-MS-Office365-Filtering-Correlation-Id: 9058ca05-4d2c-453e-6d7f-08dcd9c482cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: uhVArqJlAfYE07kVGJdqRSTnnRHv6892S37uoxmRQJtIr7thzlNlXPTL9Yii7s8u7UGMTZPQ05bjWHYAF9TYp9myb0BH+A/gCWTS2CxzBPRo0pphxghzroLeXDK767ZWiL0BQZAdYZhg8bvrVryDguICbUlB5S/EPDnQBlDvjgq7ogsQpN8PYdg182vbbOQI0PLKBkD4tJO+LzU3ih5s2EZKvmNCGyMz/YDzYY8srwJKiQOyNhKtxisNPQETmp0sM9RU5e+z0LfhXVUQFaCEF2KI1IXNeqDoGoKbQYag2Nh6pCXetSOdM1RPiZsfjoPM2vXgWGCMj/7lW4mgaCTkIFyLl3/bnze79OAfOz6n2sqOpOYxGs57u8z+V3TV2YAkH93GT3Qz4aVgMrGtutX7OZ2zogPhe39EnQXBB+fehzFdtvxstHsvYs9Diult3cNQMjGfQ1zZlyfOG+YOFSJQowlBGI/OeCOxzE1Z6kuxPXdP2mq7HymhQqDkD9M+q74OSLs9LqYC8q5nyA0OrO1H0TQwhMe6OHZp3tXG8Uu44/oEebDDjyCpDi5Diu7Kp4/K6qkEm/u5QnD7bJA1mkQV9b1VKQobTYm+veVgFcE66s16TGCKTAjMei967Fj6KrFUTsPKpJOKYZzQ1Z638MMOJGtbdgUMJxOvIR6p433mNo721fN7qH16saO0Ycxo2lCHpwJWPbhHEJW9/MHconFJEcUMjTapJPlXXI1Qnc6EQCvIc8M9pM6a/3ARSSlnr0oFG6LwFzP9DVMAPkCto5hv1RxCsKfO8mCwDtzD/NaDI6X2zXeBfEf71TJ6uydDt4AChA2CIVdsg1o2dFtJJyIy4pleywNgz/Gc/ihyKHCt2JLrdg9GTzadWnMdb9Zcj4YebgcAMkEo3zEgq1gyXucBE7pTthwfcRq3BduFEXdQl69OPT/Lw1xtCF52aJ3A9Xm+i0+p74wO45+QBJp1K1zu8j7Sj4Gn/Hd3btP7ItWI7ha4s7IA2tXYfFvLtnFvwpgpWjtUldqMzElM2B1iEhbDLGHhL77d/0cwGqxh7E4bgueGdzsXK4rBjogzjWRsSSJSPY/KbAzQeHoOs9IbZRD4JBdLzj0c/G1G70uAb0EOUfxCwwnUPuzT1uDMzmatxZPZWNIU24Uc1QlQxPRZOPm3wKm+B9vDmGOs9VQHzR2uSVOWVrnW7ruLDm/8ewJeB3Ufjjz3z65k3BGTmtr3DiolZP5ERZrvOOOL/Q0Vs/9hvM2d93aON87Qf/D4L9Z+Qx9oH6SBP3hIlgEaoPn+i2HdwuC2B4ORNRC822B1Pu+uBonmjhtWxj+IJEFeAeRzYpF/9ddPDoRqKNkMXVY1BBl1cqJTSii6DLzjpY1cit19WXfDN6urN4mdyB/CaHUTTByPA9Eds/giNtJuQWZTedyVQsuulYVrXQqzKOuybtwlMAuS79NPWDvK7hn1EA0jSDtW X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:20.7830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9058ca05-4d2c-453e-6d7f-08dcd9c482cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5719 The userspace needs CXL device information, e.g. HDM decoder registers offset to know when the VM updates the HDM decoder and re-build the mapping between GPA in the virtual HDM decoder base registers and the HPA of the CXL region created by the vfio-cxl-core when initialize the CXL device. To acheive this, a new VFIO CXL device cap is required to convey those information to the usersapce. Introduce a new VFIO CXL device cap to expose necessary information to the userspace. Initialize the cap with the information filled when the CXL device is being initialized. vfio-pci-core fills the CXL cap into the caps returned to userapce when CXL is enabled. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 15 +++++++++++++++ drivers/vfio/pci/vfio_pci_core.c | 19 ++++++++++++++++++- include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 10 ++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index d8b51f8792a2..cebc444b54b7 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -367,6 +367,19 @@ static int setup_virt_comp_regs(struct vfio_pci_core_device *core_dev) return 0; } +static void init_vfio_cxl_cap(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + cxl->cap.header.id = VFIO_DEVICE_INFO_CAP_CXL; + cxl->cap.header.version = 1; + cxl->cap.hdm_count = cxl->hdm_count; + cxl->cap.hdm_reg_offset = cxl->hdm_reg_offset; + cxl->cap.hdm_reg_size = cxl->hdm_reg_size; + cxl->cap.hdm_reg_bar_index = cxl->comp_reg_bar; + cxl->cap.dpa_size = cxl->dpa_size; +} + int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) { struct vfio_cxl *cxl = &core_dev->cxl; @@ -401,6 +414,8 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (ret) goto err_enable_cxl_device; + init_vfio_cxl_cap(core_dev); + flags = VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE | VFIO_REGION_INFO_FLAG_MMAP; diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index e0f23b538858..47e65e28a42b 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -963,6 +963,15 @@ static int vfio_pci_info_atomic_cap(struct vfio_pci_core_device *vdev, return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); } +static int vfio_pci_info_cxl_cap(struct vfio_pci_core_device *vdev, + struct vfio_info_cap *caps) +{ + struct vfio_cxl *cxl = &vdev->cxl; + + return vfio_info_add_capability(caps, &cxl->cap.header, + sizeof(cxl->cap)); +} + static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, struct vfio_device_info __user *arg) { @@ -984,9 +993,17 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, if (vdev->reset_works) info.flags |= VFIO_DEVICE_FLAGS_RESET; - if (vdev->has_cxl) + if (vdev->has_cxl) { info.flags |= VFIO_DEVICE_FLAGS_CXL; + ret = vfio_pci_info_cxl_cap(vdev, &caps); + if (ret) { + pci_warn(vdev->pdev, + "Failed to setup CXL capabilities\n"); + return ret; + } + } + info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index e5646aad3eb3..d79f7a91d977 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -80,6 +80,7 @@ struct vfio_cxl { struct resource ram_res; struct vfio_cxl_region region; + struct vfio_device_info_cap_cxl cap; }; struct vfio_pci_core_device { diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 0895183feaac..9a5972961280 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -257,6 +257,16 @@ struct vfio_device_info_cap_pci_atomic_comp { __u32 reserved; }; +#define VFIO_DEVICE_INFO_CAP_CXL 6 +struct vfio_device_info_cap_cxl { + struct vfio_info_cap_header header; + __u8 hdm_count; + __u8 hdm_reg_bar_index; + __u64 hdm_reg_size; + __u64 hdm_reg_offset; + __u64 dpa_size; +}; + /** * VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8, * struct vfio_region_info)