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Fri, 20 Sep 2024 15:34:51 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 01/13] cxl: allow a type-2 device not to have memory device registers Date: Fri, 20 Sep 2024 15:34:34 -0700 Message-ID: <20240920223446.1908673-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|DM6PR12MB4138:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ea9ad7c-e11e-48ce-84d3-08dcd9c47a4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: 3XUeIwtZp6c8mDklwZSH8NSgId07HnE86ZMlV10zXgtEdFv92LqHT2w6JE4KWVD/efZ4Puk9zqgV2FdGlatxsWH57Wrygo0xeMYXnILaAyFIfPCJRLhGv36ud9eu8NEXV3CC+ClR0V80kW+pDcjcN6LJn1nNU5iV39aGnvhVDA2Fw9kpBy3YpLLtZ8QXwf/H7bXdQr1KrgU34X5I6a0E4SGU26JhPWCeouXXui19CXifVLN3FDJz3kweumIFiorIQ/DMZhW2MJrYBn9aIn9uUzitR5ED0U8kLz8xfr8YQDn5qCJPFWXZVDT0kOwO5S0avcsnb7eE7SzTUKIsYwCpInd8ZdKkjMTwMCIkShrfjUX/Y3NEXVry7xqryr/ZG46Sz8YVy8sDq2E4BF/x6kXBhAlAuuVYnCkDWl719QqQOSQFpo/UxP3E1fYilOGcWL3ga8BoHnwCS3oRhh6FsHH92g5mL8qo/NMTNq9crBS6CqVmuctlgXjmTW2pRaWyvO0x+WI7zd29+6q9YYt0PKLE0kxFk+Tqj6piXfpKcG6srmjcjHA7FYoep9jW6ByC+AadVtdX/wKJiVOrglOJR48pY8tx7dL+ZQnGNM4BnealeY+IKM8F+JMkuPjbbZCFsKRzTXoXq/FsXzw/T6QUbXYFqAKV+Olj+uRAegn4eRg197KQOeHZYs4/DXwuBLv1QSiRi3sqz4KHYR1Fo55you1YOW2T99+zeX2fbnpfF9Qmpu95BLYsMQ6SqRNQnlfh7f3JQljQ3Fn+74dt6CIiSqf+Zs7Y+YjnaQfy/8JU0YlnTLMlKGPmANQkqFZ2vRg/4FA5lk8ZTZXAI3HjiAbxEh4eloAcWi/ZSAeDVNCX07EVcPVkPmEmRkY6wi+BeLPmmX2+C4oP7hVYdbAxKcroTVl46oQ2y8h83vK8PHHg9xOq2iNvLK3DzVNRA1HJ02Zuvr4KJ2z3Ah6hjV6SaWuDh3+6+4VpxuOY8Ke1uryWPnZi/WbJSk4aKZfuNZQxePYcfiCAUlq2poBAGD+2mFnU0vW13HO3929AYHPTHqElKWaCJMQMz7PrRXT8N87A/nDVS3b3GhoCUpCcq37RqUYEZFmvzypccdYIeMN5cY/A55W1DRd8cw9XlGJDfvcSvLJIQeYpiN5XtlVkyWWvWeD/tfUTKu8Mdk/Ul8t1K2mr/1aiGTPRHo6S6jqe88XyRB6RDVb1wdPhGzsIhRE2p7/S/qrjNz12IfUpI+tJEQiet/085/KpqQ6Mf2TlqLjJLL7FIu8c7wgd/fmk6huEi+uQvtV0pTf03s7OZmHR9PQHANoMfjVv+T3auFgggIO+UHJHUACIUi1hHiBynMYhX2vktk6nnPdlZyiTVzU4bpLJUYCce0uza9QUuN7r4F/xrq7hA/Bs X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:06.7613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ea9ad7c-e11e-48ce-84d3-08dcd9c47a4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4138 CXL memory device registers provide additional information about device memory and advanced control interface for type-3 device. However, it is not mandatory for a type-2 device. A type-2 device can have HDMs but not CXL memory device registers. Allow a type-2 device not to hanve memory device register when probing CXL registers. Signed-off-by: Zhi Wang --- drivers/cxl/pci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index e00ce7f4d0f9..3fbee31995f1 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) int rc; rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, - cxlds->capabilities); - if (rc) - return rc; - - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); - if (rc) - return rc; + cxlds->capabilities); + if (!rc) { + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); + if (rc) + dev_dbg(&pdev->dev, + "Failed to map device registers.\n"); + } rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &cxlds->reg_map, cxlds->capabilities);