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Fri, 20 Sep 2024 15:34:52 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 02/13] cxl: introduce cxl_get_hdm_info() Date: Fri, 20 Sep 2024 15:34:35 -0700 Message-ID: <20240920223446.1908673-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|PH8PR12MB6817:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ea38c5f-0a95-4e0f-fd43-08dcd9c47b41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: TPrJNDXkePvuaTF2/wTYvuQIkKOecXYxExRsJlD0lGbqt1zlQhkgCeJOVXZeRIL1TZHQ54oahaoIfkrruGwXXcQx7RAlDBQbsvw06qRdi5Q3MXP4OxHjKnUFjO8h9ii03PA1qRVoRvS0IxP3pv4PwhG8lqCO8I++iziaNgm2QGS1+tpB1FoAYcPEn6BJ7pE09+PMWcq5AXijDJ/4TsG2O7e5juYc8pqPhNo91fLLVK9F8ZgfC3iCt5cGWZ6oNPGUq0pfT/IH1DTu4zg4GzFGjcHO1kP8SM0SAg9GO6j4WBU4jDoQrIq0RvWQduC9GrFI4M1CvzYJiQJMvvfJ5J2HLZEbV3VaWNATJI0mlYq05wPTtGH0R13xNtd5qpoZrN2O/QZjIRgDK/TuMcE3HKXB3GIxrG/ezPpYCM1I1LHTKeGW77B0Dtke6kGzuOIxm46izjgoZhdmn32UXr3c7DSCChpgvLLtWGF1/vx4IbW4uprucRblReGXnsqpbKKvoooYi2R3ba3fYMbAbc66EYQSYWUpRZ+8VPftiyO1TKDjDATyq16zFzg0NVuM0IjRdixCIipzs+ockuzfe4ZJie1/K4lvtJSKK6JOptz1jfL2qpPTnh78lqSK1EZXUo9k2Hc5k08S6k4W4hVThzg9FEtcsIF0r4uf947GgrkBzszmM+xVo/e8AnkqKMfnVah3O0CHfO/wX3Q9iisLG8yMKiO9yVg5AjPyLcyK2kj+FG2cDRfV5u4sfNFKYYdo4mpPX+vtKjKhPT5T8vxSJgfu4+Pb5dViq6dO8H2X5li4p+NSPlE/3dQvKQw+625l80qtCQdXYY5XQve6CJL398vjSkZM5IaTCHjfkeYYnpXOxAaR9aLjbjdYp3CGvBXyz2AR8Xas7kUcDpzyfMRVtGIv1+ldlKUyEamzKz/XRKzXxoDCAYT5Xqzo4c2zes8mntXv3aDHqmCVWwUt+JvKcla5IEuSFsog8q3NS8Gt77xoOOs5Rq3tXLkLBvfBgqDDmG4rFJMNiIE6A2iILEFvhfxv4JSn+xhnNp7QtwlhF8FCwVx5e7zqqZZ5eRyNfavOyHI+eg9CyjNVU3wP2Y41Jy2lb/TXD/wubyf5veQxQVpfOE7k7rC41k31XTo4oWY/VcgspniDB0QReT+WJ0GUHPYcerwnGfkicXaqkkcmaQ0ZKpnEP80NBaJbmXzkttQvQhB6bUOpWY9QOElxprSCL1y0gENmmYRbi4SLwaXCYa2CV0nKU+THR7zRodtY6PlM0haZbC+zUFUWy+euajGzVZi6zt0QB0LzRQjGbNpZ8clgzgHL3BkPfzQi7aeJhtRVKafW4PdoU7zHDXVaTn1gocCrmOIaTarw8Wuc8+JYfUsT4P92rOenUi885o791kvof3bEHkOycgV3a4paScyNFxbE9S+Hg/t/YCaVneEVWl3kyaYuaJXSGYoZ4qdfFxc99K8oxHDz X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:08.3726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ea38c5f-0a95-4e0f-fd43-08dcd9c47b41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6817 CXL core has the information of what CXL register groups a device has. When initializing the device, the CXL core probes the register groups and saves the information. The probing sequence is quite complicated. vfio-cxl requires the HDM register information to emualte the HDM decoder registers. Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM register information in the CXL core. Thus, it doesn't need to implement its own probing sequence. Signed-off-by: Zhi Wang --- drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ include/linux/cxl_accel_mem.h | 2 ++ 3 files changed, 33 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a663e7566c48..7b6c2b6211b3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size) +{ + struct pci_dev *pdev = to_pci_dev(cxlds->dev); + int d = cxlds->cxl_dvsec; + u16 cap; + int rc; + + if (!cxlds->reg_map.component_map.hdm_decoder.valid) { + *hdm_reg_offset = *hdm_reg_size = 0; + } else { + struct cxl_component_reg_map *map = + &cxlds->reg_map.component_map; + + *hdm_reg_offset = map->hdm_decoder.offset; + *hdm_reg_size = map->hdm_decoder.size; + } + + rc = pci_read_config_word(pdev, + d + CXL_DVSEC_CAP_OFFSET, &cap); + if (rc) + return rc; + + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL); + #define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..8d4458f7e45b 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -129,4 +129,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); + +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif /* __CXL_PCI_H__ */ diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h index 5d715eea6e91..db4182fc1936 100644 --- a/include/linux/cxl_accel_mem.h +++ b/include/linux/cxl_accel_mem.h @@ -55,4 +55,6 @@ struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd, int cxl_region_detach(struct cxl_endpoint_decoder *cxled); int cxl_accel_get_region_params(struct cxl_region *region, resource_size_t *start, resource_size_t *end); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif