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Fri, 20 Sep 2024 15:34:57 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 06/13] vfio/pci: expose vfio_pci_rw() Date: Fri, 20 Sep 2024 15:34:39 -0700 Message-ID: <20240920223446.1908673-7-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992B:EE_|DS0PR12MB7654:EE_ X-MS-Office365-Filtering-Correlation-Id: de1e1571-85bf-4dd7-a5d9-08dcd9c47d59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: OkkQAh4gOGSmRqhFTHXY/j/D5eZH8D2X0HKtfRj4LTUqomP7qNbVIl4BMs13pKGhhLfNxMCWpwQVCsa3czf1il5YYJ06ev63fF9/YfumeJJlc/HYYmNNnVFKv7aapT86GgayxqpO0mzjY3yKYFGh89VK+h8Aeb3VD8tfPFrcH+lzj+Y+HKfOBGgM4o9GOJPG1uQVP4hhI5TusATG1BRlKoHs2OC+DymN+7EUHsIKHisUwhb8ynVj/Rnr4uRjuvhrKihc8tE3yHQHrXqvRldqODkc5xIeTXv9FBEaOs0LGQbr2PBd4l7dcv/FdCal8PvReupa3mAjG2DFp7D+k/4jci9+gCz0+kuh4aMcKf3p+ZKiol876A2f0UVnJF+DWTt6k/5MbCE3Sbx9qWBC8v+Ae5b3/gpQ9dv5raME2RrgpgBAGgAS9jk3YeQ2J2VHqJ6GcojQPdv7m7IkEaIfyUIBl5xfLDg5fHqs77KV7WR/gleGzMqCObyTrjpjTuXThLa0P4bl/i3uR5ZjE0ecNrh4/1G7EYyXVOom96q2c7E+AV9kBejkLi8Eokgt3M/BdNKbqikjw5YDZmtS8zEU2qgUgxrOzvlr9aIPZtpcHqyI2/ycZyZoL54s9pfnXw13eW4itYdy/Dbz4DxhK7yA2l+HMKq0gOCAmoUqyBmeUnL/NpRJl+uEfdqL6yGGgO4gyyFBjIEZAmimG2qHAkmX8R+1RYKL8RHu8QNRtSRU5sVlv5zLlTyfehc7ZiaSx8NFQFuQer79UUiL26GRgO/QYrteRUpMGowmeJ/+rAGC8Hu+oVPAWZL8EiykWLWnt/hulstaqcw5BHnnP5na8gOvh9uHwX3oqIymouV6nKxdjUE+YeA/fLGPGPe8ulRsPviDRZRon6DOz1SdgO+qUx3nXSUH3ZXeQcH/IPscmQ7i0ySDuhWD6VcVIlvaH9VFwKQJ4fIdSKy6RO669FXiiRtY4T5hY2AEuSuWsAFkPx4wSmjU+vDymYNazWDOSUfZ2eOKAWdRi0FZXUKbJ+nbY4n999c0r+l6C/Y3/OHi1+1zOB+TrHIZ40On8XtTe4UWxipNFqlTGmYd4/EGS2i0NjG3cB760R8znevmvacIYXcMUDqCRXFJ7hLAl/uTwUKXgJavbibtWVxfnFxvl9NLeNDj/b2vVAHbCqg2bSQdzddGzrzurOi7+X+cL7JH5RsK60fmJADaWd6RPKDXnAry+gW0wGLN/OD81b4+ZA0WSZw8Ksg9DFS3W0iBZQXkxMfjces3nVjHwhLXQfXFBty2lF+iXWQHJojmeda5UNb3MNeFCzinI80KASu05MZ0JNKGxEro6XRAx9WbvmVFJfLbbw4VpErPNQq2K5N7hvalV4WqkcbaKcRqELbUT/9tEClsuQwny1iIeR1pmvVPYVqimnhzvNpyXBHmW2oOQodyePly+N+tYAtBynW2u1OwdHf4QUuM5nq4 X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:11.7737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de1e1571-85bf-4dd7-a5d9-08dcd9c47d59 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7654 vfio_pci_rw() is the common function for handling PCI device read and write. A CXL device programming interface is built on top PCI interfaces. Expose vfio_pci_rw() for vfio-cxl-core to handle the access not interesting for it. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_pci_core.c | 5 +++-- include/linux/vfio_pci_core.h | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index ba0ce0075b2f..9373942f1acb 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1537,8 +1537,8 @@ int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, } EXPORT_SYMBOL_GPL(vfio_pci_core_ioctl_feature); -static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, - size_t count, loff_t *ppos, bool iswrite) +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite) { unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); int ret; @@ -1583,6 +1583,7 @@ static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, pm_runtime_put(&vdev->pdev->dev); return ret; } +EXPORT_SYMBOL_GPL(vfio_pci_rw); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 6523d9d1bffe..62fa0f54a567 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -144,6 +144,8 @@ long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd, unsigned long arg); int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, void __user *arg, size_t argsz); +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __user *buf,