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Sun, 22 Sep 2024 05:50:27 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , Subject: [RFC 12/29] nvkm/vgpu: introduce GSP RM control interface for vGPU Date: Sun, 22 Sep 2024 05:49:34 -0700 Message-ID: <20240922124951.1946072-13-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922124951.1946072-1-zhiw@nvidia.com> References: <20240922124951.1946072-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|DS0PR12MB6557:EE_ X-MS-Office365-Filtering-Correlation-Id: 44283285-a986-4122-cdae-08dcdb052957 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: cRFZ9Jyf2MaZCKQS+rUTIhUcfuERrZY6HsVThmGIdZp10AQiTivx80bdlFWfx3Ga3L6HXdHQFX50H/FCjeKPGtWrACDr1sn0pQbVo4LH6I/f0NDIml3oN06q7aYFfVbMQlNzuytDUXRwmF//xcQCzb+knv1BvhycKWlt5Vp5U4vQl81AULEQF5AGyqQpz25qzOFquez0vyjULFTaC0HPvIelURithh877wcCNiYI1UxPeCgct2nnmqJH/eU+WDkZ1XPwakFge9FywFwT54IZmFkSMUZ4BEfMK71esrbV0QOUrBAWB3JOYkwajwuDimOU1JwlEmEWzYcCAGv1AC1FPV9Pnqln4tiYwLDEWOpy1qDsThDbiN69Ou7Q9R9BiZFUs/HYfB6oQH+adWpC5NtNiuG9oyu81Hh+IejWBP8H1dFC+81zJOIKShmOPrRH6967413DBd2GrXMvea9jlfxhs6mjffOxtV2o5UytqaZRKMJitaNgZlF+A3ynZ0oPIOevnLNHD6sgNXekQutJ0auWqVZHWK+3T25gWL5g5j69SJqagVMcr/c8pRabQaDmiKmu4CdMBWE9FjEho/0xeFXRcw1uJ8G/BnAuEfCx8KRoTxLUVML8KdTqWK+vWofxIEjbh5KxwTfk/u+3axkGYvgA+TaUFgBcPxicUjxXSr/YxU2uLgb/K28edTqO69ek8Lrp312Ckt+gStHvl2hkf6zYtgxkUOgS1kL577fvWe9caZk8KYybkI2n+DUJ1bcHDvziqq0l6enQYrVlAbchum57KiQoV/KWtrbjJ0oZSpm7y+5bMr1W38M9+5x8sg5YXwOYJmgE5KNzaJfs/NmLK1/Do384YwUpC3NcKldVZfv0Ngqn4c16oivbkgvT3Wn1Db86Kj19EeIYXOg246OJi4v6s7YYx6pFy3tmVeKtnNJ0V739nIMP3KkKHkAsKvvy6VupReEt8GK7McnE6O4uM7xTpjkYz7eK7C8GH5LV8zb1pdXbNvmiPizYHDHc4n96MxAmQwcU51ON8wG1PDsk2f3hx/OhVBQ85ah+c3vINzgyywm4ba03HbmkbjhL6bnas8zuTCEmpodcRogEXRYD089Ka4e9B2niGmO7tQSp7BVs7+lmwuN4IuY+R7HbhVR5X7clxXeU/ekmL2K0vDtBf1gnmfxJvFivyKr3DQG8HgujTYYVjM8COoDCmjF+59iCNHUsjPngXKHiX8KnAJT7BPJws7MimtH//HptZE7S4eQ8MxXCwa/TFWRIcVjW2q28xZY9uS6ueYsx2g3U5zwCIWGx18Y9+Qo+hqNZ2LLH8GbC/PT+a+/En/yDNjzqGzyHJPC25uZ0xnM0RwqLlGBTApvk7V1ShomEIMh3cI0G90ErMgzJPLk5kDSLH2emHmMTkUqPImCloPO/3kx/PkSyk3F4UcDXjgmjuVRBnVAZvWWw1nWpyFwqQ0kzUfiCxEGQP4a4 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 12:50:39.2832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44283285-a986-4122-cdae-08dcdb052957 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6557 To talk to the GSP firmware, the first step is allocating a GSP RM client. The second step is issuing GSP RM controls to access the functions provided by GSP firmware. The NVIDIA vGPU VFIO module requires a GSP RM control interface to obtain the system information, create and configure vGPUs. Implement the GSP RM control interface based on nvkm routines. Signed-off-by: Zhi Wang --- drivers/gpu/drm/nouveau/nvkm/vgpu_mgr/vfio.c | 34 ++++++++++++++++++++ include/drm/nvkm_vgpu_mgr_vfio.h | 8 +++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/vgpu_mgr/vfio.c b/drivers/gpu/drm/nouveau/nvkm/vgpu_mgr/vfio.c index a0b4be2e1085..9732e43a5d6b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/vgpu_mgr/vfio.c +++ b/drivers/gpu/drm/nouveau/nvkm/vgpu_mgr/vfio.c @@ -98,6 +98,36 @@ static u32 get_gsp_client_handle(struct nvidia_vgpu_gsp_client *client) return c->object.handle; } +static void *rm_ctrl_get(struct nvidia_vgpu_gsp_client *client, u32 cmd, + u32 size) +{ + struct nvkm_gsp_device *device = client->gsp_device; + + return nvkm_gsp_rm_ctrl_get(&device->subdevice, cmd, size); +} + +static int rm_ctrl_wr(struct nvidia_vgpu_gsp_client *client, void *ctrl) +{ + struct nvkm_gsp_device *device = client->gsp_device; + + return nvkm_gsp_rm_ctrl_wr(&device->subdevice, ctrl); +} + +static void *rm_ctrl_rd(struct nvidia_vgpu_gsp_client *client, u32 cmd, + u32 size) +{ + struct nvkm_gsp_device *device = client->gsp_device; + + return nvkm_gsp_rm_ctrl_rd(&device->subdevice, cmd, size); +} + +static void rm_ctrl_done(struct nvidia_vgpu_gsp_client *client, void *ctrl) +{ + struct nvkm_gsp_device *device = client->gsp_device; + + nvkm_gsp_rm_ctrl_done(&device->subdevice, ctrl); +} + struct nvkm_vgpu_mgr_vfio_ops nvkm_vgpu_mgr_vfio_ops = { .vgpu_mgr_is_enabled = vgpu_mgr_is_enabled, .get_handle = get_handle, @@ -106,6 +136,10 @@ struct nvkm_vgpu_mgr_vfio_ops nvkm_vgpu_mgr_vfio_ops = { .alloc_gsp_client = alloc_gsp_client, .free_gsp_client = free_gsp_client, .get_gsp_client_handle = get_gsp_client_handle, + .rm_ctrl_get = rm_ctrl_get, + .rm_ctrl_wr = rm_ctrl_wr, + .rm_ctrl_rd = rm_ctrl_rd, + .rm_ctrl_done = rm_ctrl_done, }; /** diff --git a/include/drm/nvkm_vgpu_mgr_vfio.h b/include/drm/nvkm_vgpu_mgr_vfio.h index 79920cc27055..29ff9b39d0b2 100644 --- a/include/drm/nvkm_vgpu_mgr_vfio.h +++ b/include/drm/nvkm_vgpu_mgr_vfio.h @@ -27,6 +27,14 @@ struct nvkm_vgpu_mgr_vfio_ops { struct nvidia_vgpu_gsp_client *client); void (*free_gsp_client)(struct nvidia_vgpu_gsp_client *client); u32 (*get_gsp_client_handle)(struct nvidia_vgpu_gsp_client *client); + void *(*rm_ctrl_get)(struct nvidia_vgpu_gsp_client *client, + u32 cmd, u32 size); + int (*rm_ctrl_wr)(struct nvidia_vgpu_gsp_client *client, + void *ctrl); + void *(*rm_ctrl_rd)(struct nvidia_vgpu_gsp_client *client, u32 cmd, + u32 size); + void (*rm_ctrl_done)(struct nvidia_vgpu_gsp_client *client, + void *ctrl); }; struct nvkm_vgpu_mgr_vfio_ops *nvkm_vgpu_mgr_get_vfio_ops(void *handle);