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Sun, 22 Sep 2024 05:50:21 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , Subject: [RFC 04/29] nvkm/vgpu: set the VF partition count when NVIDIA vGPU is enabled Date: Sun, 22 Sep 2024 05:49:26 -0700 Message-ID: <20240922124951.1946072-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922124951.1946072-1-zhiw@nvidia.com> References: <20240922124951.1946072-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F4:EE_|IA0PR12MB7751:EE_ X-MS-Office365-Filtering-Correlation-Id: 218d2e56-2df3-4ebb-2bc4-08dcdb05241e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: J99FfgnkxePME4EdxBmarsA2VFSUad9Nd9L6FuIuZbdNt9wcQ6AbAan5NWoSA843M2MPALx8UiwH0VHjM3su80ObYsSYyED9X4xxQqrIxadTfWD/ED9gHQi3197k+H/Cklf8UEXnCf4zQxm4ZY+7xZwIzWWwEcximMCS994YJ1VQvPea7CaSGKwQDitH6lvkgQ+9ExLwb/UlUXDv5nPDl5F5B5crCfrIg7r4se37/16CyfQdx5iFpYxkVhrW+xyO3fqYFud+7BbKzFij+3jaH7+Mz/Jnj0eQlZfO1XKfK5AmrtQFLLRQ67g/LU6RPP05b0CVRAZyQ0Aoq/BD+tGLCH2FW5Ywzdi4xl2o42vg811F2rNHyENBMNA0s07vCRmJNZFAy+W+d0KYUTeX34F3q0jw94Va09/2jSXrDj4KqeWkg0i+9RM2YnrFeLVFVpXEsaCrBLwscP21QfMuNWag7fAJY8+ri4xBhvC14XjX3tW8CzBQCJhUM5KypXnk+koqQLm5AOMD/Yb/UJtTzPRRt8Cp4MUKhenIm5HYEUqiVFkvFWMa2wcPSct+x+mvQ/hsNVc5oEh/WOWa12XasYvZ55apkBGEtQaj8qVF+dgpazcUeUyvInQ6Ne8UJDFs0Qcenw2FK0VqSDT+dsnaKyCD5+eooivjouNM2W31g4qRagwsDfZrhpF4p4mRkfHzQI/QqymHtL1QbETsb/OfFi8RfUZPv90zFRTQvHFQA/aiTqJdlBxU9ZTcsDbTcsge0aX/XzHvmKVeJaIlxNKUi+6i4mo6D2DJhOoSFKk8H6ityoujNmIhcBhnKTDG7UtywRcnMWOGlATFTBxVC8o6A30qV4OluSUfsFJgGeA0Tx3dzlLaPyc2/FTbMKnzOPQUNCehKd8hOg7AGsyjRUTQUvJIpoZF+HYdAcikhr4fGpNSUV4WSJ3m5zwxIyrTz/Z2Hgm4YH0HLAm2MWtEAqc5m1GwvQHLVuJQ1CNcvKv3V54UMRXeo/s7tt8CGLN7vlE/u0RI7BeWli1DZA99CoJYbQZIwXljMqIXT1s9v1uy47BbXFwazC1vOUl66aWGQQozU8zNYLCwq/J/UkL6ElhgGpBCT9JJVaZeIlP2X3w5gAJXyvSgvyw55U3pAKtn1jnEXGhRdPlG/KoovUYkDgLVmaifboU0PndJgGLR2NDeHcfT8Mc4WoCBSwDxDuexh+Dn+G+5UUkTydvdvZHR360BGgMXf1ObMag8QLOhsppu39xpPwYOhQrqoHqeSgd/5E2d4ODSikN9E0Pyd4dXc3OUxyUnPEyDtgC6G+Q2JqA0FiVFjycWPail4R/TMMFk1Z+f530/QxDHAHxeCBfn7ef4sMxBg/6Quw27b/nXs8jkd03NWk/N79rNJjdLQO6dpZIMy/Gr X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 12:50:30.6263 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 218d2e56-2df3-4ebb-2bc4-08dcdb05241e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7751 GSP firmware needs to know the number of max-supported vGPUs when initialization. The field of VF partition count in the GSP WPR2 is required to be set according to the number of max-supported vGPUs. Set the VF partition count in the GSP WPR2 when NVKM is loading the GSP firmware and initializes the GSP WPR2, if vGPU is enabled. Cc: Neo Jia Cc: Surath Mitra Signed-off-by: Zhi Wang --- drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h index 3fbc57b16a05..f52143df45c1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h @@ -61,6 +61,7 @@ struct nvkm_gsp { } frts, boot, elf, heap; u64 addr; u64 size; + u8 vf_partition_count; } wpr2; struct { u64 addr; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c index a38a6abcac6f..14fc152d6859 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c @@ -2037,6 +2037,7 @@ r535_gsp_wpr_meta_init(struct nvkm_gsp *gsp) meta->vgaWorkspaceOffset = gsp->fb.bios.vga_workspace.addr; meta->vgaWorkspaceSize = gsp->fb.bios.vga_workspace.size; meta->bootCount = 0; + meta->gspFwHeapVfPartitionCount = gsp->fb.wpr2.vf_partition_count; meta->partitionRpcAddr = 0; meta->partitionRpcRequestOffset = 0; meta->partitionRpcReplyOffset = 0; @@ -2640,6 +2641,7 @@ r535_gsp_oneinit(struct nvkm_gsp *gsp) if (nvkm_vgpu_mgr_is_supported(device)) { gsp->fb.wpr2.heap.size = SZ_256M; + gsp->fb.wpr2.vf_partition_count = NVIDIA_MAX_VGPUS; } else { u32 fb_size_gb = DIV_ROUND_UP_ULL(gsp->fb.size, 1 << 30);