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Sun, 22 Sep 2024 05:50:22 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , Subject: [RFC 06/29] nvkm/vgpu: set RMSetSriovMode when NVIDIA vGPU is enabled Date: Sun, 22 Sep 2024 05:49:28 -0700 Message-ID: <20240922124951.1946072-7-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922124951.1946072-1-zhiw@nvidia.com> References: <20240922124951.1946072-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|CY8PR12MB7514:EE_ X-MS-Office365-Filtering-Correlation-Id: f19cb38a-ff1d-4f0d-8f60-08dcdb052773 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: 5JSFFEzvKkQypFQpN5c43RPq8H5gUx+1VHdlEXmvkISXGGcEoSoeJuc7EFkQ9yJssI7oxmXTcXUzwXYOJ1gYfiNAkQAIgw35gYmxlzkEICFW8/YBQVC+pia546VQlo1lUN+wkSqAS+3I4INqTE/glZQ6IMWP8k8Y64F5crKzAmhVgq1R5SZOZixE+oMpOepS2axnD7Isb9L35Ln7v2iQTy6WNl0dnBZBVfk5aIXAemwE77gXFNeKHK1oZHo+fNUABufTEgC73qKxwigbjdKQRfxNxMUFjQpntgn/R3oqf9iWzE74Y6FGFyy/Pl3kd3dTrUwUIfy+z7Whb86zFVlyrWjooIRsaF6SdBizeegGTxjiCwZzSzlkw3DCuWjXd6aWv3jo26qW9UrhoAzA5LyLsb864ZskSAoHjYfjkf+AOMLsrqhu2SXr6HoO//WrOUFamWnQHBCDbe7pdq766KKkg490VpzbLUQj4Kg8ZCxQK0JMTfuzVH7MBATTbPpFPOJRrY52Bj2dtRCi98ohXi8Uxto2TXEAmUssTtlcm+ok7qDr3ZMk0XFIyd6NGyemuPkFAbg46w6tFjIeFUGjozOd72IUr6knG2uEqVEzkwkVDvQ5swZR/R/xsz2uvojGAZjbKX241wmo/fXIqUFHfAJ8KciSqC7oUxOpLEFgAarIDhTOnUWltsMCbkmFlAObZdGUvhgdCad0Bsd3oaPBquK8LZPhQUokhf+BtQB4eRV5X5c57erzA/jZpy+N+pq5y4snpdQ6cw21E57vYrKt30/TpQCextE0P6XN0S2fQ6afsVY/jgYUpuRSUhjQuc6IpxZnnvTTXMU8WGWxJweeUFHNxswhoSKyQj/XjbyiZzN13/KCyAKBiX7PDMBaGTKXZpJC3VXSPERKk3rb5oByHmjJHZqgBcNNWdsf1rKJsYZGWwqXXcJUJvT/XTyf2nSuFmy+9Mk92uEFvAPNEltEG9oPCdhLWpfXQ528Yo0LSXe75ILx+xwQLb+yLlS+pv6jYS/LIYiN3Gg+xKGTd68JuiP5CimmctloAa97fQOX6wLtp6uYj3uVZ1X/mpzJJevJK4R1JGPVzdyPICEmDmAAHiF4zKgvcZrTFmzMpJqDsrzd5rhBqy55WXc2IgGFCJsbRWxeMZDd7fUclL3b8aGDHPq7pDYtynuGTOZPUnvcMEb8+CSKkM73Y2ZpRi+ZFnaBISOVgGuwZK9GwsMuZP+XAXtEjgtvIOq2Wbav0Y0JwaVl2TzUMnz45UfKTfGS61Wl1RD3k6j5L3C6qszrxDJ8VjkCD5odN14lI7hIHP8l39cTylFkHhwaHUKcPJ48CwPPDr06lUuKmoNQrPBizL2eyQpC4jrHPoDhlabut3k9xCxFsc83fhBTDKK94eDZejvVpOpw X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 12:50:36.1097 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f19cb38a-ff1d-4f0d-8f60-08dcdb052773 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7514 The registry object "RMSetSriovMode" is required to be set when vGPU is enabled. Set "RMSetSriovMode" to 1 when nvkm is loading the GSP firmware and initialize the GSP registry objects, if vGPU is enabled. Cc: Neo Jia Cc: Surath Mitra Signed-off-by: Zhi Wang --- drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c index 49552d7df88f..a7db2a7880dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c @@ -1500,6 +1500,9 @@ r535_gsp_rpc_set_registry(struct nvkm_gsp *gsp) kfree(p); } + if (nvkm_vgpu_mgr_is_supported(gsp->subdev.device)) + add_registry_num(gsp, "RMSetSriovMode", 1); + rpc = nvkm_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_SET_REGISTRY, gsp->registry_rpc_size); if (IS_ERR(rpc)) { ret = PTR_ERR(rpc);