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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000009B.mail.protection.outlook.com (10.167.244.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Mon, 21 Oct 2024 05:57:34 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 21 Oct 2024 00:56:23 -0500 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v13 04/13] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests Date: Mon, 21 Oct 2024 11:21:47 +0530 Message-ID: <20241021055156.2342564-5-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241021055156.2342564-1-nikunj@amd.com> References: <20241021055156.2342564-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|MW6PR12MB7071:EE_ X-MS-Office365-Filtering-Correlation-Id: 5624998f-8cfb-4cee-cd0f-08dcf1954293 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: ZOUO/+2QBpkgNi4NRrqQsaAK8COr0ZWG8gmw2edOw3nDE48aqWlBwINbjT3zC5HwdgaGY1Dx/jSyP8jVrMSqYN0M0XwjDhOC8ksM8xuJi2Q0I4wr/vj4pCe6ePcfZ6ytQJ5Utqv/cbyiZwXQSe8yC+9LJeOedYTsNn0h3AlQ8fkq2cX7lce6Qh1lrlhfy4CsaXTOukTKYAgZdTy4VY5CS3P9M1J0wvnEcWIxf+Snp3s5B/sHvkdjCu++h00sHqecdCGG3VtBuU+b2OeuBsrNufLqYqxqPlt8GY9royA6dBtrUUE9o48PtBA230yJzbGv6BPNuwXm/hrAvTDLRdvWcSDzTbFvxfwjdQMyn7JGynBQxG67F8f8ytc9OFYEdlJV0yc+LB1vwYup+PRjNAFbRxW89fZwfGvSkY8rwtYDKxWT9hZHrCT16W0r6bZuiWmCWoGJOT77CSJBIqqSgbeHuMUO5/gYLSt2dKSupzWsW5yPO7GMf5NpU92jAT9HckYgV0sCbih82QsbuIn2RqKn/9Lh5cpY/9jDetBS8V0Tcjb6m5+ADvQ3YWGxG79MQ6q4aoCccT9B9F43XUdTsOpGCk1EAgeRmFAkDmUIZFXki6bxLIayKR9FF9Aq2MsJO7hcalfTOJ9FAZm45nMtEv0EMw5FvFFGlmIfO89Nq6G9h5BBtXciaGcWhcpZjFda1FresM5l272qe3VHgWsqOnN9SGd90+WJLMRMlh3L9G1IDgDOcHSW4lv2THWQx3FfqXEg/LRlQiw+G7BP7S17GgPDiVnnvsIMd9s5oYxyrcfc1SEF0mqi4KeOhUrHQv47xmbmxD5JP4dsxi6fE7cWSNdhx9TSkg7EgDy61reP+HiaJcRd716Srtrexs/p698Fgvdp8lTyymlskW0yqQo6+cLnpzJZwxuoEP0cyWlDIbXSrXAPaEpVPDQN2HORIGZXmP1VWQ8u+fPYLU6L8VvbIMf1k/ZVuIvo6y2R6b65yGVhwfY0h7fNtpPVuQOQRkXnO841WcenDBmiukcV44N9XmIvqZNatMNWSNgINj2tOeDmA+LZzNTqJexcnaCjt8mL5NV93El4aTRR7iuBKKNY4ODAZlN8BecoCcqtjSXKIqoCWHHiLH6QztDjbjnn074MXlpvdg9ByvQO2qQuJ+Bkmqbvrl66qPeXJP8xR2xyqk1UYuRFVi4awaxC6fix5eZ4fWfViP2btN8QOUwUBGhPo6YKCpjE5BzNal15Cd+Pn5j5NSMOT8ywX5fjO+3xCpxqF3ZJtp6IcJT+vHysL/kVkJ4lDH6lKQGeDox314VXRCsfPHxv8wE4V6PBthW/+RrYH330nNV7z0wnKyO7SpUxTIn6ml3rJWX9KEm/QJ08Kkjjuhaj6VGssLI6BB1IRjPw4Ks0idS2d//sSkbP1eOC1D0Wmw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2024 05:57:34.8390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5624998f-8cfb-4cee-cd0f-08dcf1954293 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7071 Secure TSC enabled guests should not write to MSR_IA32_TSC(10H) register as the subsequent TSC value reads are undefined. MSR_IA32_TSC read/write accesses should not exit to the hypervisor for such guests. Accesses to MSR_IA32_TSC needs special handling in the #VC handler for the guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored, and reads of MSR_IA32_TSC should return the result of the RDTSC instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky Tested-by: Peter Gonda --- arch/x86/coco/sev/core.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 965209067f03..2ad7773458c0 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -1308,6 +1308,30 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) return ES_OK; } + /* + * TSC related accesses should not exit to the hypervisor when a + * guest is executing with SecureTSC enabled, so special handling + * is required for accesses of MSR_IA32_TSC: + * + * Writes: Writing to MSR_IA32_TSC can cause subsequent reads + * of the TSC to return undefined values, so ignore all + * writes. + * Reads: Reads of MSR_IA32_TSC should return the current TSC + * value, use the value returned by RDTSC. + */ + if (regs->cx == MSR_IA32_TSC && cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) { + u64 tsc; + + if (exit_info_1) + return ES_OK; + + tsc = rdtsc(); + regs->ax = UINT_MAX & tsc; + regs->dx = UINT_MAX & (tsc >> 32); + + return ES_OK; + } + ghcb_set_rcx(ghcb, regs->cx); if (exit_info_1) { ghcb_set_rax(ghcb, regs->ax);