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AJvYcCVf2Q1cCK8lOJsAphIL+VZjnwRbEsZUh3xkx40W10tMU8V+mrhSWOdbtbabCbVXVt5nNBw=@vger.kernel.org X-Gm-Message-State: AOJu0YwdguEES5S6OwNskmY6MhgP7W297GqvQCMX+IieeyI6oX+HqAEy dw8vTSLIvrGS4xUMOSpLOm1ndLjrl2KYPU10ZR9ucWON8vgNgCIf5kh+fvtzmGrxKgi4rp+d731 cQOjQFA== X-Google-Smtp-Source: AGHT+IGzqRDsg2PzRLzqCFl7gr4a8ftn+I8+zYOg3xTOpEKFCEBYRQxWqZwKNprPXM6RvFGVT+CQWKASwGCx X-Received: from rananta-linux.c.googlers.com ([fda3:e722:ac3:cc00:11b:3898:ac11:fac1]) (user=rananta job=sendgmr) by 2002:a02:a613:0:b0:4db:e3a0:c40e with SMTP id 8926c6da1cb9f-4dc44251858mr9721173.0.1729558038062; Mon, 21 Oct 2024 17:47:18 -0700 (PDT) Date: Tue, 22 Oct 2024 00:47:09 +0000 In-Reply-To: <20241022004710.1888067-1-rananta@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241022004710.1888067-1-rananta@google.com> X-Mailer: git-send-email 2.47.0.105.g07ac214952-goog Message-ID: <20241022004710.1888067-3-rananta@google.com> Subject: [kvm-unit-tests PATCH 2/3] arm: fpu: Convert 'q' registers to 'v' to satisfy clang From: Raghavendra Rao Ananta To: Subhasish Ghosh , Joey Gouly , Andrew Jones Cc: Oliver Upton , Marc Zyngier , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Clang doesn't seem to support 'q' register notation in the clobbered list, and hence throws the following error: arm/fpu.c:235:3: error: unknown register name 'q0' in asm fpu_reg_read(outdata); ^ arm/fpu.c:59:10: note: expanded from macro 'fpu_reg_read' : "q0", "q1", "q2", "q3", \ ^ arm/fpu.c:281:3: error: unknown register name 'q0' in asm fpu_reg_write(*indata); ^ arm/fpu.c:92:10: note: expanded from macro 'fpu_reg_write' : "q0", "q1", "q2", "q3", \ ^ 2 errors generated. Hence, replace 'q' with 'v' registers for the clobbered list. Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore") Signed-off-by: Raghavendra Rao Ananta --- arm/fpu.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arm/fpu.c b/arm/fpu.c index edbd9a94..587b6ea3 100644 --- a/arm/fpu.c +++ b/arm/fpu.c @@ -56,16 +56,16 @@ static inline bool arch_collect_entropy(uint64_t *random) "stp q30, q31, [%0], #32\n\t" \ : "=r" (__val) \ : \ - : "q0", "q1", "q2", "q3", \ - "q4", "q5", "q6", "q7", \ - "q8", "q9", "q10", "q11", \ - "q12", "q13", "q14", \ - "q15", "q16", "q17", \ - "q18", "q19", "q20", \ - "q21", "q22", "q23", \ - "q24", "q25", "q26", \ - "q27", "q28", "q29", \ - "q30", "q31", "memory"); \ + : "v0", "v1", "v2", "v3", \ + "v4", "v5", "v6", "v7", \ + "v8", "v9", "v10", "v11", \ + "v12", "v13", "v14", \ + "v15", "v16", "v17", \ + "v18", "v19", "v20", \ + "v21", "v22", "v23", \ + "v24", "v25", "v26", \ + "v27", "v28", "v29", \ + "v30", "v31", "memory"); \ }) #define fpu_reg_write(val) \ @@ -89,16 +89,16 @@ do { \ "ldp q30, q31, [%0], #32\n\t" \ : \ : "r" (__val) \ - : "q0", "q1", "q2", "q3", \ - "q4", "q5", "q6", "q7", \ - "q8", "q9", "q10", "q11", \ - "q12", "q13", "q14", \ - "q15", "q16", "q17", \ - "q18", "q19", "q20", \ - "q21", "q22", "q23", \ - "q24", "q25", "q26", \ - "q27", "q28", "q29", \ - "q30", "q31", "memory"); \ + : "v0", "v1", "v2", "v3", \ + "v4", "v5", "v6", "v7", \ + "v8", "v9", "v10", "v11", \ + "v12", "v13", "v14", \ + "v15", "v16", "v17", \ + "v18", "v19", "v20", \ + "v21", "v22", "v23", \ + "v24", "v25", "v26", \ + "v27", "v28", "v29", \ + "v30", "v31", "memory"); \ } while (0) #ifdef CC_HAS_SVE