From patchwork Tue Oct 22 13:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13845708 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 248AA19CC3E for ; Tue, 22 Oct 2024 13:36:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729604220; cv=none; b=T60i8MWDiQuRoBlBVvn6F9A2giFj1Jy5ZQh4mhOEuNarmsMG6NeAKuoVepdv9qWn6QKzRMwCKJHfx4291E1SbpISFCKO7YVDVqj22S+7Wcj52fY9ynLOAvcTBojfGpem9lQoAEHguUAbWVgUv7ocKx4Jz/WvN4uGrgwWPeaIclE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729604220; c=relaxed/simple; bh=TEjT9vfLlCt/Mc8nTWxqbY6vNGP1X8MOONe4ssw/sls=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sBgGMUKZluqUp2uz0pDAKFzta2pkdzb0f3uLkWX2xQtCdttmpuzMVRNR3JoTpzbwbN07dAVOd1W8yuUNtmMnd0AdZLkTi3354j8GXKaQirwJjOM0FX3hDWx4odjTgcWnhTAthXffl5dmgCHxPdMveCdVk3jEsDqRDf2sy+y+z1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TXUkOZ3h; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TXUkOZ3h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729604219; x=1761140219; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TEjT9vfLlCt/Mc8nTWxqbY6vNGP1X8MOONe4ssw/sls=; b=TXUkOZ3hd/qt5CzSejKNF8Qr2+jtXShdB1aQqaZv5yOMb9A+2Z/9G4rM w5CWa2aQSgRfTQ0efMa/PNfNAKOoKMmZ+pE7B7kWlkf2G98j8/KV4M51n O71MezTHJe1Zhm7pJQcYUa/ARlxBbYxFJZAwYw7Fj8jqlVon4AApavWz6 Ur60sbXH+rZitXH+4kul60s3rTYa7Z2c6+oQQG/yWjMemNLuZfABRhfY5 yQhDfEnOAWblpoUCXqPK7gVjPbDYSDqh0Y3LKgpcDFX0SxaVrKgzGt++d OgaPnqxRay9257+YGbWwZUhJ2ytY5fETLzMIYbHYKTJzC6lAjDi7996K0 Q==; X-CSE-ConnectionGUID: rbznWbj2SDidyZnPuqV/HA== X-CSE-MsgGUID: MoQpUj+TRzqxw1eON2BbWw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46603792" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46603792" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 06:36:58 -0700 X-CSE-ConnectionGUID: 0mi/KwG8SrmbGUlx6dY4Bw== X-CSE-MsgGUID: QFOw/PCjSN68kmzEB8qccw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="79782484" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa009.jf.intel.com with ESMTP; 22 Oct 2024 06:36:53 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Date: Tue, 22 Oct 2024 21:51:51 +0800 Message-Id: <20241022135151.2052198-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022135151.2052198-1-zhao1.liu@intel.com> References: <20241022135151.2052198-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 640b2114b429..6ae7c4765402 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -324,6 +324,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches = true; return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index 192f78539a6e..e6680701eec3 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b6e12b46c9cc..9a81402e71c4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7884,13 +7884,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + MachineClass *mc = MACHINE_GET_CLASS(ms); - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } qemu_register_reset(x86_cpu_machine_reset_cb, cpu);