From patchwork Tue Oct 22 13:51:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13845707 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C4919CC3E for ; Tue, 22 Oct 2024 13:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729604214; cv=none; b=mZkhuqkJvY1jOB8a0JA0Npr86F6r/5o8IB2wva936WsL7GYNjji3hRRN+p9YMv6wZmup1OpAgTVcnEE4OrtbzB3ss998PrPdRzO1bYmpSNDKtR5Jg/mCS1Ox44XnxHqfJMHZqCp+PVJV8drPh0yOH66EHKhkE0UtjT1gOYjDAd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729604214; c=relaxed/simple; bh=Dp1CRpbyNbOs2HtP+ckcBp2tV2Btqa2nfJTthkEGR/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NsQxWwpeFPjsbCC0Ri95yq2Wxh3xkxItmnL5Tiys8VmU2FRZQKhL/cZA/2ppBijsEhd+sDUDaN3cvRQOVyfU6jnImYIQAlqR+Zc+0HWOP657KE9sVHe1sxNIJQXt8MFCry0t2jYQd+DcdtJX/NMNVNC1qSaFXJ9BN89Tjga+dXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dtvsb/kE; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dtvsb/kE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729604213; x=1761140213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Dp1CRpbyNbOs2HtP+ckcBp2tV2Btqa2nfJTthkEGR/I=; b=dtvsb/kEpVJcblPxyEiPztOA+bFGqdeaQrGY3jyye/HsnUK/dcrOO1tn MhkcJv9Ok966abwQ2sQOa1IRTVEAqQa5CWFag0dfPB02MQtKHCG8BxiPX 3UYQzc5CbOSi5T0dUvVWnpMfOXvZkaYlZGc0vq87kd9OUALqorndOcaPC /sxMqR7Cncy0qiRfjs6Y0WsJpqZcU8YeO876lB2aPyL043XuI+3Dldkay GdSbDNiCf86V0v9GcKGuZ7fNCreswmkvVh/k0e5ATbG/SEjLKSSupbAMN p/zC6edBUJNSykPeffTWEYZx92Ul/AkeftZkyTtGYvkvIZ0vlB8dnwF+q g==; X-CSE-ConnectionGUID: bL1UV7QeToK7enHfW2BnZg== X-CSE-MsgGUID: wmJXFb1+TBeIvStTzZNWnw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46603758" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46603758" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 06:36:52 -0700 X-CSE-ConnectionGUID: nCL6oB2DT6iTPNbEDHvEzA== X-CSE-MsgGUID: Rd6tQNijTiOTRl85kSgJ/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="79782452" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa009.jf.intel.com with ESMTP; 22 Oct 2024 06:36:47 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu , Yongwei Ma Subject: [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Date: Tue, 22 Oct 2024 21:51:50 +0800 Message-Id: <20241022135151.2052198-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022135151.2052198-1-zhao1.liu@intel.com> References: <20241022135151.2052198-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4cf7..8aea2308dcb9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; diff --git a/qemu-options.hx b/qemu-options.hx index daae49414740..fe39973d97a5 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=@var{} memory encryption object to use (default=none)\n" " hmat=on|off controls ACPI HMAT support (default=off)\n" " memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n" - " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n", + " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n" + " smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=]name[,prop=value[,...]]`` @@ -159,6 +160,34 @@ SRST :: -machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512 + + ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel`` + Define cache properties for SMP system. + + ``cache=cachename`` specifies the cache that the properties will be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=topologylevel`` sets the cache topology level. It accepts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a special + value ``default``. If ``default`` is set, then the cache topology will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding CPU + topology level. For example, ``topology=core`` makes the cache shared + by all threads within a core. The omitting cache will default to using + the ``default`` level. + + The default cache topology model for an i386 PC machine is as follows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core ERST DEF("M", HAS_ARG, QEMU_OPTION_M,