From patchwork Fri Nov 1 08:33:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13858904 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99DEA156C70 for ; Fri, 1 Nov 2024 08:16:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730449011; cv=none; b=DC84ZMJJ77R/a64GtrJrSMk/aMi/4aR28CXRGtOxSNe2kX+0mNVOais5dIWb3xbwiD0LHSM5OC+mSNtdpiTOYGkuRuKDVG6/80QjHGCFepJ3IkhayVTuqjY8exlhB7J+wlJDgF9y1olkB+kuZKKHUpP1v2TU8q/7/T8AcO2krUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730449011; c=relaxed/simple; bh=se3A3A+kRvSwSAobc6tYFr7xeZZ8F/aVOqRAc4gXB10=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bHBB099K5zhld+sjI2iZyVY94trwwShdNTspk+v9c5J/T+Z+KyCGisVdCY+KkZVrU0XgDCIlK4Msxt7KZEiW8P4vAW29aInRU0ZvJCHpu4KYIMOwqa4m//eV2ziVfQOtTxNdxi7AYxGeLxsVBzJJ0RdBzfSsY17xGN/fw7XSS0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=M22CeVWp; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="M22CeVWp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449010; x=1761985010; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=se3A3A+kRvSwSAobc6tYFr7xeZZ8F/aVOqRAc4gXB10=; b=M22CeVWpsOgRrXv/VRnuNY+CMWDdaDhYN0I1BnMv86GdEjbgpFKLREF2 DUxuz2HjMe97YxYICYfrmlOlPylmwgnCcZ8aLzCeYbD+3VfCCqTOcmnBC tOHXchbo3IBPcelw/ojPPwoj69YVrv5kAqh06bQ4PL6EPvcYo5D8v1QeB i482qRosIjvQKdiHScyWGGB9KxOSMZ6+eQOFWgfvccfeliWAFxFc4RxVN N5TfKHiztksMS/Azj4fftaurhS8R5SgbwcKcztG4ZStQgUD4ggHofeoXO eNm7KHuNq928ysadxTy0okncoGb4HesoPWU/J7SViR2KGQuJyQdO8xfhz A==; X-CSE-ConnectionGUID: VFoQ8r59QjSZ4PfAPPLr9Q== X-CSE-MsgGUID: 1LFJlYVFTHSYEqSigtlD/g== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846101" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846101" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:50 -0700 X-CSE-ConnectionGUID: MfnoaelzSjKKq1CkEaOG1g== X-CSE-MsgGUID: DHNWzy+0SfuGlV9pH5NKow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834736" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:44 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v5 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Date: Fri, 1 Nov 2024 16:33:31 +0800 Message-Id: <20241101083331.340178-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 640b2114b429..6ae7c4765402 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -324,6 +324,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches = true; return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index e07fcf0983e1..2d650bbf13c4 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1cf4cda1e647..49f19f896197 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8035,13 +8035,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + MachineClass *mc = MACHINE_GET_CLASS(ms); - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } qemu_register_reset(x86_cpu_machine_reset_cb, cpu);