From patchwork Fri Nov 1 08:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13858899 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E979149C47 for ; Fri, 1 Nov 2024 08:16:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730448984; cv=none; b=SJfhsUQj7KMRj8ReWB7W/diui5QTHhtrt9fb+20fOhE9qsxsB4+ZwcncS+qeocE9re5ETUPIsbEVU/4guNpcLFQMe/7PNq+1UbFVAsYTOo4MLVgKOkFPtZJGOdnFq2xuHPV/J4pLN44AuPHCoP9u7KnuQrWDBaq3zKcYCUgAG5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730448984; c=relaxed/simple; bh=E+zkEptv6x8nT44rXYHjEFJL+24l6aO0fCh+CMO/upA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZmWarDg1AviqzNd1LucPlFvvKdUNDTnIoEhXg4KPux1sMtiKfhnTwVtabUahFA1vwVWkiGM1KIqa+tTwTCzXSFWe1Ls24HAv7dV/08a04VI5eM6DyTrG/C53tMNdD0L+hQNC/riyCZHn9n3Z7VxEplM3+Z0r1YBw8wNzgDpprxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h0H6p1az; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h0H6p1az" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448982; x=1761984982; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E+zkEptv6x8nT44rXYHjEFJL+24l6aO0fCh+CMO/upA=; b=h0H6p1azppQuDh5k8BFg1Fap6hCEZNlHyIyQJO6RdRwOF9RQbbNiSx1l X7Y2PszdRhhwVUOeSIWenjZNWZjVRwLS48gt+r7n6zyz6TOUmVNCJKCwA fVjzPGnn9tzIwXHXDtGvNeLhV5xWLJJziv2IYvTqLWGe8gkcWS9OSNEGg jYbc+850XP4I5KiV5LqeYs3DDxGeYr+lIbJZp35awkGNLCgRWbZ3m6bf/ 1cpFxoiQ6RtZglekEyLKn6fp9BLvvKEfRkQ41dLBoXuWAIKpHRF0J5p+p 3mqGNq/N+f+obGH44CfxD9yo47/gkho3I5V4z3F9DkGNkV7SFcqBUZ1gY Q==; X-CSE-ConnectionGUID: Z/IaKSWQQM+BRK6ra3Diwg== X-CSE-MsgGUID: LMdtYqpGQnS6ygNyqcRW9Q== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846041" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846041" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:22 -0700 X-CSE-ConnectionGUID: lbUxUVPyRUaFO+h8PpQtzg== X-CSE-MsgGUID: j7+CQvoERvCthoCj5OUWJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834611" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:16 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 4/9] hw/core: Check smp cache topology support for machine Date: Fri, 1 Nov 2024 16:33:26 +0800 Message-Id: <20241101083331.340178-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Dropped cache level check because if some fields is marked as default, then we can't guarentee the hierarchies are correct. (Daniel) --- hw/core/machine-smp.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 +++ 2 files changed, 44 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index c6d90cd6d413..ebb7a134a7be 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,32 @@ void machine_parse_smp_config(MachineState *ms, } } +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) || + (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) || + (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc = MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); @@ -283,6 +305,25 @@ bool machine_parse_smp_cache(MachineState *ms, set_bit(node->value->cache, caches_bitmap); } + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props = &ms->smp_cache.props[i]; + + /* + * Reject non "default" topology level if the cache isn't + * supported by the machine. + */ + if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index f12a727b4008..cda12070fc52 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -153,6 +153,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -162,6 +164,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; /**