From patchwork Fri Nov 1 08:33:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13858901 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED2B4839F4 for ; Fri, 1 Nov 2024 08:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730448994; cv=none; b=OQE57F8FCZwMOkYSa9RHAUcSljazb5P44bz+7we7jwVRNYdyl/OVAkJz/eEnoMIPuxvUGRzflguHT9JYsI5rjRgEajW5qU3rFaR1wpI1mMd6KDKUJAZ9+izlzVXrpfhfXIKxCPcCzwKUsiwoUaGOVlWe4KnbcchDPot/Ex9j0Dg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730448994; c=relaxed/simple; bh=EGbj8vANOciytGjaNrt6k0e5IUuBc6pcu0CAwcWWiBE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OZuCeJiDEIN4ykk11JivSVU6c7JqToEHcUU9uX2SeY4LyLI0BjflB0E3wM05wCgtTiLQHNt964CW2gvgj61tyUvsYNjNHLskgDoWQVYSfK4qv5B7g1FDpLF+sKG3+dgWekc7hV5StMV3b41eUcMztIuf74KEjoze4wtdgBt1DAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bR/1lfUr; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bR/1lfUr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448993; x=1761984993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EGbj8vANOciytGjaNrt6k0e5IUuBc6pcu0CAwcWWiBE=; b=bR/1lfUrzGED17znPKbfUj4PV0h7Fw7LXaLJz9pg+DhaxWo+WV91Szi0 0o8OOnzYiXfYJnjfnSRIbESo5puIn6+01FOt6hslqqtCR7W2cCwJOnzuP 3Ib8vxGlIBFtfdRyHNwCs7A4ofg+ylje84SEKJWS/MQYYi94tOderu8zk SnrlJyC1AwSozPP4Ub0cLne7QfQ9GB0/l+rXX5x4nu9I8hR21+WdaVFLc BXy+ErE2WTxmIqS/URpo9YXWtwlCj/EjaD27pApOMYbBoB5DjJhR1jMo4 WSuLWut1kbJpZjBRZT9ch3EXB9H5f4D9UMXlwkxhgQa2GvzW9AVN5THH4 w==; X-CSE-ConnectionGUID: qlHFwpBLTgOU7nVl87A4hw== X-CSE-MsgGUID: dbde14oEToqWKev1Wg5EMA== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846066" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846066" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:33 -0700 X-CSE-ConnectionGUID: dcN29vuBQH2Be9GsJjYitw== X-CSE-MsgGUID: uZqiM3dqRvOYw1MHcf0HIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834642" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:27 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 6/9] i386/cpu: Support thread and module level cache topology Date: Fri, 1 Nov 2024 16:33:28 +0800 Message-Id: <20241101083331.340178-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d46710a4030f..09aaed95a856 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,9 +243,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -253,10 +259,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); }