From patchwork Fri Nov 1 08:33:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13858903 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05354156C71 for ; Fri, 1 Nov 2024 08:16:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730449006; cv=none; b=gs+HBv1mzYnG1eJbCtJ6UpVWiRy1aKgFdcGjiruioD9QMAuTWmw/8pnUfvX/0vxHrOEE+HoS0+X57DchL2XJoSCHsqwpDHSEb91qktFXHJ/Uq4/DLy8yoj3TGEopJS7IhFd3pnIH0mLGLQiddWt8+k984gV0dOWRyg/GyZPfmys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730449006; c=relaxed/simple; bh=Xc0ZEM0XRjIyyn7cTteAHDQNg/ftofpyLFroEACPy64=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BPv9l0kDrQXb4Wer33BRP9HNwIowdMggJdkbL5mxRi7ehZmH8indNNCozyMt2iHADCpXS9eUe5IpO8a+lQfLj2vA5/ziYWLh8NHIx2P5kaqKgGhmJ03wD2jFhA/yub4yg9ohB5+da9MY9XkgyM9eb7n8wgqjvAKAKA0OuB3B/Ac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=X36VvoE9; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="X36VvoE9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449004; x=1761985004; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xc0ZEM0XRjIyyn7cTteAHDQNg/ftofpyLFroEACPy64=; b=X36VvoE9UxnExTMOmZpavEYwrHOjdfqb+7Euxewi3bS0nl8dczV0Apt8 menVXEHTdjM59PHkIF1DEaPZjHHEC5kuLMw3w3erUOg92VHrsKFvEFaOx lY8nkK4PJ549sBIiRNZA6Uhx5IVCPQLHd9fAC72y1Q9d31vRj61enKZH9 +KS3X4Q1pOql6C1VQ2sgExYMtZ3QMq6V7Vu00IHhcJogEbDopAVeanGMZ Y1Gi7pkmA+bI1xJIujC7YlrisoxxpGFFMPJVIesEHuB6LL+E9P/hk2D+l nV2ni6IS1cxpfHYzvGy8ws3WwjpoIACVSbkiCqEIZy2PUIecuss0ZJTok Q==; X-CSE-ConnectionGUID: A8sLH3T7SLq89aRgPh4Wqg== X-CSE-MsgGUID: qeIJpibgRoOWuqdrpjFgwg== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846086" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846086" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:44 -0700 X-CSE-ConnectionGUID: zrHITGPaQaSKU2H21ONDUg== X-CSE-MsgGUID: NfCN/3W3RXSTpoIvp8AN+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834717" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:38 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 8/9] i386/pc: Support cache topology in -machine for PC machine Date: Fri, 1 Nov 2024 16:33:30 +0800 Message-Id: <20241101083331.340178-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4cf7..8aea2308dcb9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; diff --git a/qemu-options.hx b/qemu-options.hx index dacc9790a4b8..a18ed4a9a853 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=@var{} memory encryption object to use (default=none)\n" " hmat=on|off controls ACPI HMAT support (default=off)\n" " memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n" - " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n", + " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n" + " smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=]name[,prop=value[,...]]`` @@ -159,6 +160,34 @@ SRST :: -machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512 + + ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel`` + Define cache properties for SMP system. + + ``cache=cachename`` specifies the cache that the properties will be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=topologylevel`` sets the cache topology level. It accepts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a special + value ``default``. If ``default`` is set, then the cache topology will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding CPU + topology level. For example, ``topology=core`` makes the cache shared + by all threads within a core. The omitting cache will default to using + the ``default`` level. + + The default cache topology model for an i386 PC machine is as follows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core ERST DEF("M", HAS_ARG, QEMU_OPTION_M,