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Mon, 4 Nov 2024 02:23:10 -0800 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V1 vfio 3/7] virtio: Manage device and driver capabilities via the admin commands Date: Mon, 4 Nov 2024 12:21:27 +0200 Message-ID: <20241104102131.184193-4-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20241104102131.184193-1-yishaih@nvidia.com> References: <20241104102131.184193-1-yishaih@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|CY8PR12MB7563:EE_ X-MS-Office365-Filtering-Correlation-Id: 311a6d0c-9e54-4115-58e2-08dcfcbab73e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|30052699003|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: 1ZArFkDi3erFsPOhPl0+hEH645ILOhJ78NbQwMBTMFmV8EjNRp+BADc8ROC1hayMMSDoGhyBTvYomZW/w5lYotFtbxxDNnCePhJbYOu5oc5UHLCkIz7j+3UT5jBKHNZxz9pk9w7B7ZuSYVlIMGWh5fccLdfaWY2JTd3Mg2m0f/9RWWFRHfesc63sNJQOtlUL7EXPFdDChhvAKerD/55+1LTvymlwd0fbpaOsEPaRq6BnpuMekmM8kuq7yry+4HQ9W8Gd1MVlcim1ZVyMS0SkoXsahRl1dUffG6Ckk/qBEuJydgvERVv7V2a6wJyrKs+QrhpUiHhHgEb2tD+i8vNfvC8qmPItpWkoYqrVC4gky1PCpaAAMICTkUiUSgaHgn/IfGXZjIvMzKvwQE+V5BIaS/McOMDG6uURQizTeDrlg1PKKEoM+goqTPJ/dULSnjNGm+NTiGs0F2En1825q0hWduJAy+JgsPlDczIWJ9MWnCt0KfXO9fFHXkCx2+/VA2YUMeOwDmG1nfyng0FjG2RK9E18UvAg8MXDe7ZDNVGgF0bxsX27od4+CprA1AiZMVFMtDsASPXvi2qLIln1LR60O8zzMFgoopgLhjI8WqoGOllf/czQNLNo13+oLansRrY2UIewGhzghPBxv+5aSwzblIKC5d1JsyTde0Wn35R+jJI5W7Qurc+HnEg+7ydcN8QVdI/X+qVhLpi5ccwx2B7Futn4nJK/vc32GhExo4GPnKaVtkQBj+tKEjivD+pp8XiRRJ8Cd9UlOLwWJyFV/ygGL4pF2CrrezR46BLUZUt6K95KuaHvd6SnleqY4562BjoVbSmebpuC70tyDIFQ+D0PjXMUHMHY8WMzhcKZH6t8lcEV8UEKxFBVasoodhswEHFYSZdpOVQNmSeJrfy3LadaHLtyWG/3rvWvffjj23TG1sx38epFbpvOzlpwjVWPH/nQ4b/WkfctCSw6oTn0s0ErULySjq8w+gfD5uOiPsPCP3zShWqedyAofvfXUqX2KvcHXz9XU6rXTDbDSqkzS/41+LkMYK2kkZ+BE0iRpTpgNlcA7oOIvrUgQoiGVnky0OgKOD/NVAQYnUrn+G3Rs21e8qKK7j47EBE3A3jKt4xby6pqNxPPFdgDWqqjnCTPhnGUglPtrY+qps68McNBw8RWJMGJw/OBs6oix3+jUyxj2YuXWoiGuIb77iy0fXWEKh717qUaJr/x+KXJBSV8ZdEvYcbDlLqqKI42wnS2hg15d2D02zI8Lbv4CPPFeVeNfYTEdzYUeYszdRKfcsnTebfdjWBUI9bOLkO1ShTb76q2fEpCt7UVoCZreqE4gXuLEkC9jwoplSgSzn3VA8vjUk/CG2osC8OW9Q8Il770L0CiKLC+RZzc1pUSYNuCASjmFRVRA13LP8UaqnSOpaoMJ91VoQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(30052699003)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2024 10:23:24.6638 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 311a6d0c-9e54-4115-58e2-08dcfcbab73e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7563 Manage device and driver capabilities via the admin commands. The device exposes its supported features and resource object limits via an administrative command called VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY, using the 'self group type.' Each capability is identified by a unique ID, and the driver communicates the functionality and resource limits it plans to utilize. The capability VIRTIO_DEV_PARTS_CAP specifically represents the device's parts resource object limit. Manage the device's parts resource object ID using a common IDA for both get and set operations. Signed-off-by: Yishai Hadas --- drivers/virtio/virtio_pci_common.h | 13 +++- drivers/virtio/virtio_pci_modern.c | 105 +++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index 1d9c49947f52..04b1d17663b3 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -48,6 +48,9 @@ struct virtio_pci_admin_vq { /* Protects virtqueue access. */ spinlock_t lock; u64 supported_cmds; + u64 supported_caps; + u8 max_dev_parts_objects; + struct ida dev_parts_ida; /* Name of the admin queue: avq.$vq_index. */ char name[10]; u16 vq_index; @@ -167,15 +170,21 @@ struct virtio_device *virtio_pci_vf_get_pf_dev(struct pci_dev *pdev); BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ) | \ BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO)) +#define VIRTIO_DEV_PARTS_ADMIN_CMD_BITMAP \ + (BIT_ULL(VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY) | \ + BIT_ULL(VIRTIO_ADMIN_CMD_DRIVER_CAP_SET) | \ + BIT_ULL(VIRTIO_ADMIN_CMD_DEVICE_CAP_GET)) + /* Unlike modern drivers which support hardware virtio devices, legacy drivers * assume software-based devices: e.g. they don't use proper memory barriers * on ARM, use big endian on PPC, etc. X86 drivers are mostly ok though, more * or less by chance. For now, only support legacy IO on X86. */ #ifdef CONFIG_VIRTIO_PCI_ADMIN_LEGACY -#define VIRTIO_ADMIN_CMD_BITMAP VIRTIO_LEGACY_ADMIN_CMD_BITMAP +#define VIRTIO_ADMIN_CMD_BITMAP (VIRTIO_LEGACY_ADMIN_CMD_BITMAP | \ + VIRTIO_DEV_PARTS_ADMIN_CMD_BITMAP) #else -#define VIRTIO_ADMIN_CMD_BITMAP 0 +#define VIRTIO_ADMIN_CMD_BITMAP VIRTIO_DEV_PARTS_ADMIN_CMD_BITMAP #endif void vp_modern_avq_done(struct virtqueue *vq); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index 487d04610ecb..8ddac2829bc8 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -230,12 +230,117 @@ static void virtio_pci_admin_cmd_list_init(struct virtio_device *virtio_dev) kfree(data); } +static void +virtio_pci_admin_cmd_dev_parts_objects_enable(struct virtio_device *virtio_dev) +{ + struct virtio_pci_device *vp_dev = to_vp_device(virtio_dev); + struct virtio_admin_cmd_cap_get_data *get_data; + struct virtio_admin_cmd_cap_set_data *set_data; + struct virtio_dev_parts_cap *result; + struct virtio_admin_cmd cmd = {}; + struct scatterlist result_sg; + struct scatterlist data_sg; + u8 resource_objects_limit; + u16 set_data_size; + int ret; + + get_data = kzalloc(sizeof(*get_data), GFP_KERNEL); + if (!get_data) + return; + + result = kzalloc(sizeof(*result), GFP_KERNEL); + if (!result) + goto end; + + get_data->id = cpu_to_le16(VIRTIO_DEV_PARTS_CAP); + sg_init_one(&data_sg, get_data, sizeof(*get_data)); + sg_init_one(&result_sg, result, sizeof(*result)); + cmd.opcode = cpu_to_le16(VIRTIO_ADMIN_CMD_DEVICE_CAP_GET); + cmd.group_type = cpu_to_le16(VIRTIO_ADMIN_GROUP_TYPE_SRIOV); + cmd.data_sg = &data_sg; + cmd.result_sg = &result_sg; + ret = vp_modern_admin_cmd_exec(virtio_dev, &cmd); + if (ret) + goto err_get; + + set_data_size = sizeof(*set_data) + sizeof(*result); + set_data = kzalloc(set_data_size, GFP_KERNEL); + if (!set_data) + goto err_get; + + set_data->id = cpu_to_le16(VIRTIO_DEV_PARTS_CAP); + + /* Set the limit to the minimum value between the GET and SET values + * supported by the device. Since the obj_id for VIRTIO_DEV_PARTS_CAP + * is a globally unique value per PF, there is no possibility of + * overlap between GET and SET operations. + */ + resource_objects_limit = min(result->get_parts_resource_objects_limit, + result->set_parts_resource_objects_limit); + result->get_parts_resource_objects_limit = resource_objects_limit; + result->set_parts_resource_objects_limit = resource_objects_limit; + memcpy(set_data->cap_specific_data, result, sizeof(*result)); + sg_init_one(&data_sg, set_data, set_data_size); + cmd.data_sg = &data_sg; + cmd.result_sg = NULL; + cmd.opcode = cpu_to_le16(VIRTIO_ADMIN_CMD_DRIVER_CAP_SET); + ret = vp_modern_admin_cmd_exec(virtio_dev, &cmd); + if (ret) + goto err_set; + + /* Allocate IDR to manage the dev caps objects */ + ida_init(&vp_dev->admin_vq.dev_parts_ida); + vp_dev->admin_vq.max_dev_parts_objects = resource_objects_limit; + +err_set: + kfree(set_data); +err_get: + kfree(result); +end: + kfree(get_data); +} + +static void virtio_pci_admin_cmd_cap_init(struct virtio_device *virtio_dev) +{ + struct virtio_pci_device *vp_dev = to_vp_device(virtio_dev); + struct virtio_admin_cmd_query_cap_id_result *data; + struct virtio_admin_cmd cmd = {}; + struct scatterlist result_sg; + int ret; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return; + + sg_init_one(&result_sg, data, sizeof(*data)); + cmd.opcode = cpu_to_le16(VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY); + cmd.group_type = cpu_to_le16(VIRTIO_ADMIN_GROUP_TYPE_SRIOV); + cmd.result_sg = &result_sg; + + ret = vp_modern_admin_cmd_exec(virtio_dev, &cmd); + if (ret) + goto end; + + /* Max number of caps fits into a single u64 */ + BUILD_BUG_ON(sizeof(data->supported_caps) > sizeof(u64)); + + vp_dev->admin_vq.supported_caps = le64_to_cpu(data->supported_caps[0]); + + if (!(vp_dev->admin_vq.supported_caps & (1 << VIRTIO_DEV_PARTS_CAP))) + goto end; + + virtio_pci_admin_cmd_dev_parts_objects_enable(virtio_dev); +end: + kfree(data); +} + static void vp_modern_avq_activate(struct virtio_device *vdev) { if (!virtio_has_feature(vdev, VIRTIO_F_ADMIN_VQ)) return; virtio_pci_admin_cmd_list_init(vdev); + virtio_pci_admin_cmd_cap_init(vdev); } static void vp_modern_avq_cleanup(struct virtio_device *vdev)