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Wed, 13 Nov 2024 03:52:40 -0800 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V4 vfio 1/7] virtio_pci: Introduce device parts access commands Date: Wed, 13 Nov 2024 13:51:54 +0200 Message-ID: <20241113115200.209269-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20241113115200.209269-1-yishaih@nvidia.com> References: <20241113115200.209269-1-yishaih@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|LV3PR12MB9438:EE_ X-MS-Office365-Filtering-Correlation-Id: 3eb5c45a-a56c-469b-43d9-08dd03d9b5d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: hH4GosGVHBF2cq8VSrp98ziJmbFyjhrzYSl2JEbktRmZE2kzNdqMrUMbtm8j93i6/g9RNBRc9l0FLHSf21U8Pp9caVo5MwSOzs3/0lDqppw9BDdy/OQ0zoTyaDOryCpWF/QycWzekJQwgU1IwMOUDhZjaeFQCKfqvpHRwtNV27GAecuLxsLXGB1lTF8e3ZJKxW2ZouJrRxaLFRilpyBGTBRBt8x6lx8s/PVrSrzNl2dZcjA1QXvgEwdIzcuU7vaQ/AUzp06ERJNLnBrHpZGgXpmcxVtGL9QvZO27K4V5lEH4mTdPaDOTfPPtH/GBuD6twCFapuhQKWjXrpa6eQqqmdTWkpcJq87PaiXQe4nMMAMTVfkXuvKuYPjaOFp9hqoj6ynuX9lz/QOZxJ/3fb+/gJ9VLAujMhvjjg4bNjDMJXgOxfC3FkLBQjhRYzVpByUXWRmIljNUyXB5dZ2Zbo/tOGLWmJA10OQcY2euowQwbiVTbKlgEmbbMmIv6ou+MVp2xO7ZShIBf9PdRlPE04dUlzKcCon5vN6JP2RswjEPzadjBdD6J5/nlq7JwQJia4LspZZKm5JlfKeP7ZM/lgpj9+uLZ1X8ket3GPp8k5IkEmcIeuB1wopYzsIW3meJM7fBz66iUlWBvMqUjYxVmm7pzwmmN1g7uYBrp0oDKg473tkyaY/iHPabA/Gh3GmOYtmmantVQMAvt3UL6OlqagLyQ09CJqA0JHWjcxf7F/2lvkA8+gIL2zzVjenrloqccJXr+YXkjnlOl0LRQHikt5zw43OSC9KK+SKcd1wO4TOxSU8YuAXasB0z9d22Xw6W+cd0usGu/kj2MT5rmDcYrifcylQQTIEKjfow0f4jhncdb5OEGgE8eRTdNb4MIS3MH0tosGZM9UNMPUcd1PZsSfShXMu+ul7tod6P8Xef7kaJpwyYZX0E0vJQ3jOT0yDnukwjw2LzPsQcV1B1NElGWWEQKQFKG7J3UjSSodx4sia6duvCGDcW5RuRFp11bnCWlK5K4EXNmqT1DGV3R4MmD3qR2mecC/f5pjUwLDfRUT/IB5EgR6cxD/uL14NQDQnl2XhFIUYMHdyihgXWC322omfJomE89HOTxfiwVIvzOSITdqjpS/SeAcLMrvrpIwMDXMhyYhGwU0fbPEbKHbOQ2p+zg+vFMhU6PZhb+EkAS3ZVwLerdDzBCJZ8wXiDATpv0MnLF6nGSUWLW/f+6ePQrlHd5jN+dVkGk2Yk5V1jyC3IOO9LPaGlG4gWtSfnb6nZheXQYSqGAVim5Ab3J/7TmYZtKZwAjJGO1VDQ8IQQIH+/vkKxpRFst2Ld7OMPWUrXQMLXDhYTN/XtmwwKPYVQZ+pqx+bieBb/kLvywyet0qlvd3FCdmW3nHOrPLSMrlFxV6fMGg87Y+sG2atxh5jpABumyA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 11:52:54.8929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3eb5c45a-a56c-469b-43d9-08dd03d9b5d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9438 Introduce device parts access commands via the admin queue. These commands and their structure adhere to the Virtio 1.4 specification. Acked-by: Michael S. Tsirkin Signed-off-by: Yishai Hadas --- include/uapi/linux/virtio_pci.h | 131 ++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index a8208492e822..1beb317df1b9 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -40,6 +40,7 @@ #define _LINUX_VIRTIO_PCI_H #include +#include #ifndef VIRTIO_PCI_NO_LEGACY @@ -240,6 +241,17 @@ struct virtio_pci_cfg_cap { #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5 #define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6 +/* Device parts access commands. */ +#define VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY 0x7 +#define VIRTIO_ADMIN_CMD_DEVICE_CAP_GET 0x8 +#define VIRTIO_ADMIN_CMD_DRIVER_CAP_SET 0x9 +#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE 0xa +#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY 0xd +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET 0xe +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET 0xf +#define VIRTIO_ADMIN_CMD_DEV_PARTS_SET 0x10 +#define VIRTIO_ADMIN_CMD_DEV_MODE_SET 0x11 + struct virtio_admin_cmd_hdr { __le16 opcode; /* @@ -286,4 +298,123 @@ struct virtio_admin_cmd_notify_info_result { struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO]; }; +#define VIRTIO_DEV_PARTS_CAP 0x0000 + +struct virtio_dev_parts_cap { + __u8 get_parts_resource_objects_limit; + __u8 set_parts_resource_objects_limit; +}; + +#define MAX_CAP_ID __KERNEL_DIV_ROUND_UP(VIRTIO_DEV_PARTS_CAP + 1, 64) + +struct virtio_admin_cmd_query_cap_id_result { + __le64 supported_caps[MAX_CAP_ID]; +}; + +struct virtio_admin_cmd_cap_get_data { + __le16 id; + __u8 reserved[6]; +}; + +struct virtio_admin_cmd_cap_set_data { + __le16 id; + __u8 reserved[6]; + __u8 cap_specific_data[]; +}; + +struct virtio_admin_cmd_resource_obj_cmd_hdr { + __le16 type; + __u8 reserved[2]; + __le32 id; /* Indicates unique resource object id per resource object type */ +}; + +struct virtio_admin_cmd_resource_obj_create_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __le64 flags; + __u8 resource_obj_specific_data[]; +}; + +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS 0 + +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_GET 0 +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_SET 1 + +struct virtio_resource_obj_dev_parts { + __u8 type; + __u8 reserved[7]; +}; + +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_SIZE 0 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_COUNT 1 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_LIST 2 + +struct virtio_admin_cmd_dev_parts_metadata_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __u8 type; + __u8 reserved[7]; +}; + +#define VIRTIO_DEV_PART_F_OPTIONAL 0 + +struct virtio_dev_part_hdr { + __le16 part_type; + __u8 flags; + __u8 reserved; + union { + struct { + __le32 offset; + __le32 reserved; + } pci_common_cfg; + struct { + __le16 index; + __u8 reserved[6]; + } vq_index; + } selector; + __le32 length; +}; + +struct virtio_dev_part { + struct virtio_dev_part_hdr hdr; + __u8 value[]; +}; + +struct virtio_admin_cmd_dev_parts_metadata_result { + union { + struct { + __le32 size; + __le32 reserved; + } parts_size; + struct { + __le32 count; + __le32 reserved; + } hdr_list_count; + struct { + __le32 count; + __le32 reserved; + struct virtio_dev_part_hdr hdrs[]; + } hdr_list; + }; +}; + +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_SELECTED 0 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_ALL 1 + +struct virtio_admin_cmd_dev_parts_get_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __u8 type; + __u8 reserved[7]; + struct virtio_dev_part_hdr hdr_list[]; +}; + +struct virtio_admin_cmd_dev_parts_set_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + struct virtio_dev_part parts[]; +}; + +#define VIRTIO_ADMIN_CMD_DEV_MODE_F_STOPPED 0 + +struct virtio_admin_cmd_dev_mode_set_data { + __u8 flags; +}; + #endif