[RFC,14/15] vfio: enable IOMMU_TYPE1 for RISC-V

Message ID	20241114161845.502027-31-ajones@ventanamicro.com (mailing list archive)
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Headers	show Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F5D1AC88A for <kvm@vger.kernel.org>; Thu, 14 Nov 2024 16:19:11 +0000 (UTC) From: Andrew Jones <ajones@ventanamicro.com> To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 14/15] vfio: enable IOMMU_TYPE1 for RISC-V Date: Thu, 14 Nov 2024 17:18:59 +0100 Message-ID: <20241114161845.502027-31-ajones@ventanamicro.com> In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	iommu/riscv: Add irqbypass support \| expand [RFC,00/15] iommu/riscv: Add irqbypass support [RFC,01/15] irqchip/riscv-imsic: Use hierarchy to reach irq_set_affinity [RFC,02/15] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP [RFC,03/15] irqchip/riscv-imsic: Add support for DOMAIN_BUS_MSI_REMAP [RFC,04/15] iommu/riscv: report iommu capabilities [RFC,05/15] iommu/riscv: use data structure instead of individual values [RFC,06/15] iommu/riscv: support GSCID and GVMA invalidation command [RFC,07/15] iommu/riscv: Move definitions to iommu.h [RFC,08/15] iommu/riscv: Add IRQ domain for interrupt remapping [RFC,09/15] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch [RFC,10/15] RISC-V: KVM: Add irqbypass skeleton [RFC,11/15] RISC-V: Define irqbypass vcpu_info [RFC,12/15] iommu/riscv: Add guest file irqbypass support [RFC,13/15] RISC-V: KVM: Add guest file irqbypass support [RFC,14/15] vfio: enable IOMMU_TYPE1 for RISC-V [RFC,15/15] RISC-V: defconfig: Add VFIO modules

Message ID

20241114161845.502027-31-ajones@ventanamicro.com (mailing list archive)

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Headers

From: Andrew Jones <ajones@ventanamicro.com>
To: iommu@lists.linux.dev,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: tjeznach@rivosinc.com,
	zong.li@sifive.com,
	joro@8bytes.org,
	will@kernel.org,
	robin.murphy@arm.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	tglx@linutronix.de,
	alex.williamson@redhat.com,
	paul.walmsley@sifive.com,
	palmer@dabbelt.com,
	aou@eecs.berkeley.edu
Subject: [RFC PATCH 14/15] vfio: enable IOMMU_TYPE1 for RISC-V
Date: Thu, 14 Nov 2024 17:18:59 +0100
Message-ID: <20241114161845.502027-31-ajones@ventanamicro.com>
In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com>
References: <20241114161845.502027-17-ajones@ventanamicro.com>
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Series

iommu/riscv: Add irqbypass support | expand

Commit Message

Andrew Jones Nov. 14, 2024, 4:18 p.m. UTC

From: Tomasz Jeznach <tjeznach@rivosinc.com>

Enable VFIO support on RISC-V architecture.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 drivers/vfio/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index ceae52fd7586..ad62205b4e45 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -39,7 +39,7 @@  config VFIO_GROUP
 
 config VFIO_CONTAINER
 	bool "Support for the VFIO container /dev/vfio/vfio"
-	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
+	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV)
 	depends on VFIO_GROUP
 	default y
 	help

[RFC,14/15] vfio: enable IOMMU_TYPE1 for RISC-V

Commit Message

Patch