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Mon, 09 Dec 2024 20:48:24 -0800 (PST) Received: from sholland-0826.internal.sifive.com ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a9c9da809dsm17022405ab.4.2024.12.09.20.48.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Dec 2024 20:48:24 -0800 (PST) From: Samuel Holland To: kvm@vger.kernel.org Cc: Samuel Holland Subject: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries Date: Mon, 9 Dec 2024 22:44:40 -0600 Message-Id: <20241210044442.91736-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241210044442.91736-1-samuel.holland@sifive.com> References: <20241210044442.91736-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This allows flat binaries to be understood by U-Boot's booti command and its PXE boot flow. Signed-off-by: Samuel Holland --- riscv/cstart.S | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/riscv/cstart.S b/riscv/cstart.S index b7ee9b9c..106737a1 100644 --- a/riscv/cstart.S +++ b/riscv/cstart.S @@ -39,15 +39,29 @@ * The hartid of the current core is in a0 * The address of the devicetree is in a1 * - * See Linux kernel doc Documentation/riscv/boot.rst + * See Linux kernel doc Documentation/arch/riscv/boot.rst and + * Documentation/arch/riscv/boot-image-header.rst */ .global start start: + j 1f + .balign 8 + .dword 0 // text offset + .dword stacktop - ImageBase // image size + .dword 0 // flags + .word (0 << 16 | 2 << 0) // version + .word 0 // res1 + .dword 0 // res2 + .ascii "RISCV\0\0\0" // magic + .ascii "RSC\x05" // magic2 + .word 0 // res3 + /* * Stash the hartid in scratch and shift the dtb address into a0. * thread_info_init() will later promote scratch to point at thread * local storage. */ +1: csrw CSR_SSCRATCH, a0 mv a0, a1