| Message ID | 20241210044442.91736-3-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Improved bare metal support | expand |
diff --git a/lib/riscv/io.c b/lib/riscv/io.c index b3f587bb..8d684ccd 100644 --- a/lib/riscv/io.c +++ b/lib/riscv/io.c @@ -13,6 +13,9 @@ #include <asm/setup.h> #include <asm/spinlock.h> +#define UART_LSR_OFFSET 5 +#define UART_LSR_THRE 0x20 + /* * Use this guess for the uart base in order to make an attempt at * having earlier printf support. We'll overwrite it with the real @@ -76,8 +79,11 @@ void io_init(void) void puts(const char *s) { spin_lock(&uart_lock); - while (*s) + while (*s) { + while (!(readb(uart0_base + UART_LSR_OFFSET) & UART_LSR_THRE)) + ; writeb(*s++, uart0_base); + } spin_unlock(&uart_lock); }
This is necessary when running tests on bare metal. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- lib/riscv/io.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)