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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004682.mail.protection.outlook.com (10.167.243.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8251.15 via Frontend Transport; Thu, 12 Dec 2024 20:51:01 +0000 Received: from MKM-L10-YUNXIA9.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Dec 2024 14:51:00 -0600 From: Yunxiang Li To: , CC: , , , , Yunxiang Li Subject: [PATCH 2/3] vfio/pci: refactor vfio_pci_bar_rw Date: Thu, 12 Dec 2024 15:50:49 -0500 Message-ID: <20241212205050.5737-2-Yunxiang.Li@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212205050.5737-1-Yunxiang.Li@amd.com> References: <20241212205050.5737-1-Yunxiang.Li@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|CY8PR12MB7514:EE_ X-MS-Office365-Filtering-Correlation-Id: a1f7a539-7e9b-4b0c-0920-08dd1aeeaff9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:51:01.2725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1f7a539-7e9b-4b0c-0920-08dd1aeeaff9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7514 In the next patch the logic for reading ROM will get more complicated, so decouple the ROM path from the normal path. Also check that for ROM write is not allowed. Signed-off-by: Yunxiang Li --- drivers/vfio/pci/vfio_pci_rdwr.c | 47 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index a1eeacad82120..4bed9fd5af50f 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -236,10 +236,9 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, struct pci_dev *pdev = vdev->pdev; loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; int bar = VFIO_PCI_OFFSET_TO_INDEX(*ppos); - size_t x_start = 0, x_end = 0; + size_t x_start, x_end; resource_size_t end; void __iomem *io; - struct resource *res = &vdev->pdev->resource[bar]; ssize_t done; if (pci_resource_start(pdev, bar)) @@ -253,41 +252,43 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, count = min(count, (size_t)(end - pos)); if (bar == PCI_ROM_RESOURCE) { + if (iswrite) + return -EINVAL; /* * The ROM can fill less space than the BAR, so we start the * excluded range at the end of the actual ROM. This makes * filling large ROM BARs much faster. */ io = pci_map_rom(pdev, &x_start); - if (!io) { - done = -ENOMEM; - goto out; - } + if (!io) + return -ENOMEM; x_end = end; + + done = vfio_pci_core_do_io_rw(vdev, 1, io, buf, pos, + count, x_start, x_end, 0); + + pci_unmap_rom(pdev, io); } else { - int ret = vfio_pci_core_setup_barmap(vdev, bar); - if (ret) { - done = ret; - goto out; - } + done = vfio_pci_core_setup_barmap(vdev, bar); + if (done) + return done; io = vdev->barmap[bar]; - } - if (bar == vdev->msix_bar) { - x_start = vdev->msix_offset; - x_end = vdev->msix_offset + vdev->msix_size; - } + if (bar == vdev->msix_bar) { + x_start = vdev->msix_offset; + x_end = vdev->msix_offset + vdev->msix_size; + } else { + x_start = 0; + x_end = 0; + } - done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, + done = vfio_pci_core_do_io_rw(vdev, pci_resource_flags(pdev, bar) & IORESOURCE_MEM, io, buf, pos, count, x_start, x_end, iswrite); - - if (done >= 0) - *ppos += done; - - if (bar == PCI_ROM_RESOURCE) - pci_unmap_rom(pdev, io); + } out: + if (done > 0) + *ppos += done; return done; }