Message ID | 20250103081828.7060-2-manali.shukla@amd.com (mailing list archive) |
---|---|
State | New |
Headers | show
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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD0.mail.protection.outlook.com (10.167.241.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8314.11 via Frontend Transport; Fri, 3 Jan 2025 08:18:44 +0000 Received: from chalupa-d178host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 3 Jan 2025 02:18:43 -0600 From: Manali Shukla <manali.shukla@amd.com> To: <kvm@vger.kernel.org>, <linux-kselftest@vger.kernel.org> CC: <pbonzini@redhat.com>, <seanjc@google.com>, <shuah@kernel.org>, <nikunj@amd.com>, <thomas.lendacky@amd.com>, <vkuznets@redhat.com>, <manali.shukla@amd.com>, <bp@alien8.de>, <babu.moger@amd.com> Subject: [PATCH v5 1/3] x86/cpufeatures: Add CPUID feature bit for Idle HLT intercept Date: Fri, 3 Jan 2025 08:18:26 +0000 Message-ID: <20250103081828.7060-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250103081828.7060-1-manali.shukla@amd.com> References: <20250103081828.7060-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: <kvm.vger.kernel.org> List-Subscribe: <mailto:kvm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:kvm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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Add support for the Idle HLT intercept feature
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expand
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 645aa360628d..4fef0533f764 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -386,6 +386,7 @@ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* SVME addr check */ +#define X86_FEATURE_IDLE_HLT (15*32+30) /* IDLE HLT intercept */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* "avx512vbmi" AVX512 Vector Bit Manipulation instructions*/