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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD4.mail.protection.outlook.com (10.167.241.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8335.7 via Frontend Transport; Mon, 6 Jan 2025 12:47:44 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 6 Jan 2025 06:47:38 -0600 From: Nikunj A Dadhania To: , , , CC: , , , , , , , , , Alexey Makhalov , Juergen Gross , Boris Ostrovsky Subject: [PATCH v16 11/13] x86/tsc: Upgrade TSC clocksource rating for guests Date: Mon, 6 Jan 2025 18:16:31 +0530 Message-ID: <20250106124633.1418972-12-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106124633.1418972-1-nikunj@amd.com> References: <20250106124633.1418972-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|CY5PR12MB6408:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ce75f8e-e942-4dcd-eb1d-08dd2e5050d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|7416014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2025 12:47:44.3283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ce75f8e-e942-4dcd-eb1d-08dd2e5050d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6408 Hypervisor platform setup (x86_hyper_init::init_platform) routines register their own PV clock sources (KVM, HyperV, and Xen) at different clock ratings, resulting in PV clocksource being selected even when a stable TSC clocksource is available. Upgrade the clock rating of the TSC early and regular clocksource to prefer TSC over PV clock sources when TSC is invariant, non-stop, and stable Cc: Alexey Makhalov Cc: Juergen Gross Cc: Boris Ostrovsky Suggested-by: Thomas Gleixner Signed-off-by: Nikunj A Dadhania --- arch/x86/kernel/tsc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 34dec0b72ea8..88d8bfceea04 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -274,10 +274,29 @@ bool using_native_sched_clock(void) { return static_call_query(pv_sched_clock) == native_sched_clock; } + +/* + * Upgrade the clock rating for TSC early and regular clocksource when the + * underlying platform provides non-stop, invariant, and stable TSC. TSC + * early/regular clocksource will be preferred over other PV clock sources. + */ +static void __init upgrade_clock_rating(struct clocksource *tsc_early, + struct clocksource *tsc) +{ + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR) && + cpu_feature_enabled(X86_FEATURE_CONSTANT_TSC) && + cpu_feature_enabled(X86_FEATURE_NONSTOP_TSC) && + !tsc_unstable) { + tsc_early->rating = 449; + tsc->rating = 450; + } +} #else u64 sched_clock_noinstr(void) __attribute__((alias("native_sched_clock"))); bool using_native_sched_clock(void) { return true; } + +static void __init upgrade_clock_rating(struct clocksource *tsc_early, struct clocksource *tsc) { } #endif notrace u64 sched_clock(void) @@ -1564,6 +1583,8 @@ void __init tsc_init(void) if (tsc_clocksource_reliable || no_tsc_watchdog) tsc_disable_clocksource_watchdog(); + upgrade_clock_rating(&clocksource_tsc_early, &clocksource_tsc); + clocksource_register_khz(&clocksource_tsc_early, tsc_khz); detect_art(); }