diff mbox series

[v7,1/5] hw/core/machine: Reject thread level cache

Message ID 20250108150150.1258529-2-zhao1.liu@intel.com (mailing list archive)
State New, archived
Headers show
Series i386: Support SMP Cache Topology | expand

Commit Message

Zhao Liu Jan. 8, 2025, 3:01 p.m. UTC
Currently, neither i386 nor ARM have real hardware support for per-
thread cache, and there is no clear demand for this specific cache
topology.

Additionally, since supporting this special cache topology on ARM
requires extra effort [1], it is unnecessary to support it at this
moment, even though per-thread cache might have potential scheduling
benefits for VMs without CPU affinity.

Therefore, disable thread-level cache topology in the general machine
part. At present, i386 has not enabled SMP cache, so disabling the
thread parameter does not pose compatibility issues.

In the future, if there is a clear demand for this feature, the correct
approach would be to add a new control field in MachineClass.smp_props
and enable it only for the machines that require it.

[1]: https://lore.kernel.org/qemu-devel/Z3efFsigJ6SxhqMf@intel.com/#t

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since Patch v6:
 * New commit to reject "thread" parameter when parse smp-cache.
---
 hw/core/machine-smp.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Zhao Liu Jan. 10, 2025, 7:25 a.m. UTC | #1
Hi Jonathon,

Thanks for more explaination!

Based on your clarification, I think the commit message for Patch 1
needs to be updated since I used the same wrods as the cover letter...

What about the following change?

On Wed, Jan 08, 2025 at 11:01:46PM +0800, Zhao Liu wrote:
> Date: Wed, 8 Jan 2025 23:01:46 +0800
> From: Zhao Liu <zhao1.liu@intel.com>
> Subject: [PATCH v7 1/5] hw/core/machine: Reject thread level cache
> X-Mailer: git-send-email 2.34.1
> 
> Currently, neither i386 nor ARM have real hardware support for per-
> thread cache, and there is no clear demand for this specific cache
> topology.
> 
> Additionally, since supporting this special cache topology on ARM
> requires extra effort [1], it is unnecessary to support it at this
> moment, even though per-thread cache might have potential scheduling
> benefits for VMs without CPU affinity.

Additionally, since ARM even can't support this special cache topology
in device tree, it is unnecessary to support it at this moment, even
though per-thread cache might have potential scheduling benefits for
VMs without CPU affinity.

If it's fine for u, I'll resend this series quickly.

Thanks,
Zhao

> Therefore, disable thread-level cache topology in the general machine
> part. At present, i386 has not enabled SMP cache, so disabling the
> thread parameter does not pose compatibility issues.
> 
> In the future, if there is a clear demand for this feature, the correct
> approach would be to add a new control field in MachineClass.smp_props
> and enable it only for the machines that require it.
> 
> [1]: https://lore.kernel.org/qemu-devel/Z3efFsigJ6SxhqMf@intel.com/#t
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
diff mbox series

Patch

diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index b954eb849027..4e020c358b66 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -321,6 +321,13 @@  bool machine_parse_smp_cache(MachineState *ms,
             return false;
         }
 
+        if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) {
+            error_setg(errp,
+                       "%s level cache not supported by this machine",
+                       CpuTopologyLevel_str(props->topology));
+            return false;
+        }
+
         if (!machine_check_topo_support(ms, props->topology, errp)) {
             return false;
         }