From patchwork Fri Jan 10 14:51:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13934764 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EEAB21127E for ; Fri, 10 Jan 2025 14:32:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736519580; cv=none; b=cB1iXcJfEhZEM/Bq52yP5Dmken+1DCnHUDbZ/lMRR1KBM2Ey3MmK9xAwxGYTOrocFeQKq+tmJ+KDQ5XZQUQqajgTaxOX37bzRJ3MnvSIhuJTyymVI+YzBQC4Y2tfhXfkZPZR4aH4Ye1h+ITw9CjP2d0ZZ8Bu8AsHhJtNcxichys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736519580; c=relaxed/simple; bh=shkMAuvJ+JiK4YmkroyLIrAGyT0tA05DVR9Yl2i03nc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZxQvMUlznP8sz8JaqLXDFCUrTEsdAq0utAomKrt4Q5gKtGNpIUwSH8lOXnYYL6ik2NH5Ceu3RdeXH5a14Nz7bMtYDERvi3tk1sb4YDfQ/TMQw0YI5QwJ0izou2zbKGhwDftBUeyEOUYvHTGhuWzOSZYEJQQ4IUYlhdHDiOvklR0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nyL4YDzX; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nyL4YDzX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736519578; x=1768055578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=shkMAuvJ+JiK4YmkroyLIrAGyT0tA05DVR9Yl2i03nc=; b=nyL4YDzXTW58bgUeh/1oePOEy7CKuiHygMS27wkfcNz8wbegR19ynbLy KWhfIuilUb2BYw3B07gLwbeATl41+0p9B/zbj7AsEkUvaRfO58GPSAGNe 70pXbeMj87s/9aMsQtMSAmLEGfWFuQ7teQ/Ht/Lc/W0VLd8JglFCbQovv hcoyTaw+Thti2TZMtMWcmFTYk2xf8zBHR3ln6cLF7xFvFp4Ki00lp7r4q +rIYmGHhqYUF+OLN0pSkEaqMqdfNCneeAfFEKTgkIngYa1VDy5UEo4faF mkd6xuFOJWE2EfPAajn0feCyODkV4dhFVnBwjTjv1WVa7H6ThPu8xoDGu A==; X-CSE-ConnectionGUID: +9eHlFFtT+WtvLi9pusB4w== X-CSE-MsgGUID: q2XgREvoS8y0debrlN7WvQ== X-IronPort-AV: E=McAfee;i="6700,10204,11311"; a="62185510" X-IronPort-AV: E=Sophos;i="6.12,303,1728975600"; d="scan'208";a="62185510" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2025 06:32:58 -0800 X-CSE-ConnectionGUID: 2NcUn1NuQvmTeIli9EwbPg== X-CSE-MsgGUID: 9odVbZt2TUO8rdPBwBuRkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="108790834" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa003.jf.intel.com with ESMTP; 10 Jan 2025 06:32:54 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v7 RESEND 2/5] i386/cpu: Support module level cache topology Date: Fri, 10 Jan 2025 22:51:12 +0800 Message-Id: <20250110145115.1574345-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250110145115.1574345-1-zhao1.liu@intel.com> References: <20250110145115.1574345-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow cache to be defined at the module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v6: * Dropped "thread" level cache topology support. --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 660ddafc28b5..4728373fdf03 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -247,6 +247,9 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -255,7 +258,7 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, break; default: /* - * Currently there is no use case for THREAD and MODULE, so use + * Currently there is no use case for THREAD, so use * assert directly to facilitate debugging. */ g_assert_not_reached();