From patchwork Sun Jan 12 17:08:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13936478 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB42F1C302C; Sun, 12 Jan 2025 17:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736701733; cv=none; b=TkN/eXui8jb4V1F3VxOrgz4t4E//5fWekfc4Vuq5IEGeB39xFys4ff21PfO0pocucTOSI0+2gV7KJQXNCbj4t2sFLCPr+b67lMjtt8buTaOJmL/Akcjw3cOq/8ACIckR/PBcYYQ8vQpnxfm6E35T1pd9YNTqJytVo1NYqD0w+Nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736701733; c=relaxed/simple; bh=Za1PNQ3sjrTQ/q3busy2dbutshSkyGMY6U7X8BZk2rs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XniwtdBppls9OMrwd9vQi15+Zliv9KKdMViBbJ5IMygFqxNpPmKL+i6aHqodVt51YSjYV0qmWPTZdVeAlrp72wWlFDS4XEBTvvRQqjip0XOJp1JqRpvxk1psquUrTz51ienxi36c4RqCBv19G6DfwTD4eejiraI2Cw2Icfs7qHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=akdndvHb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="akdndvHb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AD1F6C4CEE3; Sun, 12 Jan 2025 17:08:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736701733; bh=Za1PNQ3sjrTQ/q3busy2dbutshSkyGMY6U7X8BZk2rs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=akdndvHbizH1adBJFnbJdsv7SBE1JvpGTD/nHYN03vIf1KuhNHOVqxeYqUWdDxsBM nRg23H+Pk7egt2x/v8qb3qOTtA2/q+CC2L9PZxQgwY1IobgsEfAj3zCkgQ7uuAecz0 UDaZa/kPJRW+Alb6wnWE7hTy4xoJbBMMrGGlHgnOuFJnilR0AGBQat1ISRrI4qUzGk rBbiPGF3MxKdKCNmb1EN0lgZ4w/93pGgZvYIWy6oF+ddyuDsiMzaSORfbKIDmexm2/ Hpt8l6VUqpOQpQgqwGpMcj2egzBT79qWPQxY5lVCohr0h2Q95zp5XsYwnKxPIz4g5e hJgBmgxcCZjjg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tX1SF-00BNxR-VH; Sun, 12 Jan 2025 17:08:52 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Andre Przywara , Eric Auger Subject: [PATCH v2 14/17] KVM: arm64: nv: Propagate used_lrs between L1 and L0 contexts Date: Sun, 12 Jan 2025 17:08:42 +0000 Message-Id: <20250112170845.1181891-15-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250112170845.1181891-1-maz@kernel.org> References: <20250112170845.1181891-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, andre.przywara@arm.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false We have so far made sure that L1 and L0 vgic contexts were totally independent. There is however one spot of bother with this approach, and that's in the GICv3 emulation code required by our fruity friends. The issue is that the emulation code needs to know how many LRs are in flight. And while it is easy to reach the L0 version through the vcpu pointer, doing so for the L1 is much more complicated, as these structures are private to the nested code. We could simply expose that structure and pick one or the other depending on the context, but this seems extra complexity for not much benefit. Instead, just propagate the number of used LRs from the nested code into the L0 context, and be done with it. Should this become a burden, it can be easily rectified. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/vgic/vgic-v3-nested.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c index e72be14d99d55..643bd8a8e0669 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -323,6 +323,12 @@ void vgic_v3_load_nested(struct kvm_vcpu *vcpu) __vgic_v3_activate_traps(cpu_if); __vgic_v3_restore_state(cpu_if); + + /* + * Propagate the number of used LRs for the benefit of the HYP + * GICv3 emulation code. Yes, this is a pretty sorry hack. + */ + vcpu->arch.vgic_cpu.vgic_v3.used_lrs = cpu_if->used_lrs; } void vgic_v3_put_nested(struct kvm_vcpu *vcpu) @@ -358,6 +364,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) } shadow_if->lr_map = 0; + vcpu->arch.vgic_cpu.vgic_v3.used_lrs = 0; } /*