From patchwork Sun Jan 12 17:08:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13936479 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E0831C5490; Sun, 12 Jan 2025 17:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736701734; cv=none; b=Q9LQ+icEGiYh9QGcgrOwNsmP+bZQ8F/oBlI8ofFr/++vQBJ78Qddtrg3/CoHXn75WA6hS5+ipqpwppsIvT7ZHOsv9f2nb2zJu0p2n0KZDLWtdIMP8dssszUM3zNuM/ctB56/JOzlUl2oehitAnwq/EO09WqqLrT5QoBoOk8mWWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736701734; c=relaxed/simple; bh=ScLfH9JCdakxFSIYbsxrMFuSUWUanHf/RQHVMVBJ67Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iuIT88VA0fwmzL+rYwlNG5ECM/FYw/UGGfwadahD3oJhaNcvd0ZXhRlBx1YlgtcDibOpSjbJsaWmx3+B3G1lvsqj5LaP/FeRdsUOsYh4A/kPyEvSOmrv3Eps3Wjiu+b3ztXg7h9iYwtRBWAJqBx6I+Ms9ah4tYRp5tfXgSDQy5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dpSHaBub; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dpSHaBub" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EBBA8C4CEE5; Sun, 12 Jan 2025 17:08:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736701734; bh=ScLfH9JCdakxFSIYbsxrMFuSUWUanHf/RQHVMVBJ67Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dpSHaBubuSYswJKhXPXtHL0oexJif4OLuQA7fvkVo+NWFjITrGpjZ39Kh+4WbEkGr vPX3jyB6JJTAYXfE11zdnE8rwOCmDFCmEr10BA6PcQaL11iwU9iVkUNWCxvkuf09YT oXYK4Xeif4WoFAYQM+te5KhCHh7U50JNxZ2rxCXEtVGTltrogJZNk7/IYYjwWu3eDE F0sFI2cKvPKbqgtQIvkejTJEOHMeEYVjq43lJAm8ZfYSpVxnCzxe3jME17YeXitU/Q V1LADbPS1HxAt4RSSNZ7PV14L41Y68zVzyPJROCcHlrP+zIUOlHxRh2S2sk3nh/qgv WBPm83ytqUVEQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tX1SG-00BNxR-73; Sun, 12 Jan 2025 17:08:52 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Andre Przywara , Eric Auger Subject: [PATCH v2 15/17] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Date: Sun, 12 Jan 2025 17:08:43 +0000 Message-Id: <20250112170845.1181891-16-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250112170845.1181891-1-maz@kernel.org> References: <20250112170845.1181891-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, andre.przywara@arm.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Popular HW that is able to use NV also has a broken vgic implementation that requires trapping. On such HW, propagate the host trap bits into the guest's shadow ICH_HCR_EL2 register, making sure we don't allow an L2 guest to bring the system down. This involves a bit of tweaking so that the emulation code correctly poicks up the shadow state as needed, and to only partially sync ICH_HCR_EL2 back with the guest state to capture EOIcount. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/vgic/vgic-v3-nested.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c index 643bd8a8e0669..5350a4650b7a5 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -296,9 +296,19 @@ static void vgic_v3_create_shadow_state(struct kvm_vcpu *vcpu, struct vgic_v3_cpu_if *s_cpu_if) { struct vgic_v3_cpu_if *host_if = &vcpu->arch.vgic_cpu.vgic_v3; + u64 val = 0; int i; - s_cpu_if->vgic_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2); + /* + * If we're on a system with a broken vgic that requires + * trapping, propagate the trapping requirements. + * + * Ah, the smell of rotten fruits... + */ + if (static_branch_unlikely(&vgic_v3_cpuif_trap)) + val = host_if->vgic_hcr & (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 | + ICH_HCR_EL2_TC | ICH_HCR_EL2_TDIR); + s_cpu_if->vgic_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) | val; s_cpu_if->vgic_vmcr = __vcpu_sys_reg(vcpu, ICH_VMCR_EL2); s_cpu_if->vgic_sre = host_if->vgic_sre; @@ -335,6 +345,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) { struct shadow_if *shadow_if = get_shadow_if(); struct vgic_v3_cpu_if *s_cpu_if = &shadow_if->cpuif; + u64 val; int i; __vgic_v3_save_vmcr_aprs(s_cpu_if); @@ -345,7 +356,10 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) * Translate the shadow state HW fields back to the virtual ones * before copying the shadow struct back to the nested one. */ - __vcpu_sys_reg(vcpu, ICH_HCR_EL2) = s_cpu_if->vgic_hcr; + val = __vcpu_sys_reg(vcpu, ICH_HCR_EL2); + val &= ~ICH_HCR_EL2_EOIcount_MASK; + val |= (s_cpu_if->vgic_hcr & ICH_HCR_EL2_EOIcount_MASK); + __vcpu_sys_reg(vcpu, ICH_HCR_EL2) = val; __vcpu_sys_reg(vcpu, ICH_VMCR_EL2) = s_cpu_if->vgic_vmcr; for (i = 0; i < 4; i++) { @@ -354,7 +368,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) } for_each_set_bit(i, &shadow_if->lr_map, kvm_vgic_global_state.nr_lr) { - u64 val = __vcpu_sys_reg(vcpu, ICH_LRN(i)); + val = __vcpu_sys_reg(vcpu, ICH_LRN(i)); val &= ~ICH_LR_STATE; val |= s_cpu_if->vgic_lr[i] & ICH_LR_STATE;