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Tue, 14 Jan 2025 14:58:35 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f10df7asm71746105ad.47.2025.01.14.14.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 14:58:34 -0800 (PST) From: Atish Patra Date: Tue, 14 Jan 2025 14:57:35 -0800 Subject: [PATCH v2 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250114-counter_delegation-v2-10-8ba74cdb851b@rivosinc.com> References: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> In-Reply-To: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Add the description for Smcntrpmf ISA extension Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index c8685fb1fb42..848354e3048f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -135,6 +135,13 @@ properties: directlyi accessible in the supervisor mode. This extension depend on Sscsrind, Zihpm, Zicntr extensions. + - const: smcntrpmf + description: | + The standard Smcntrpmf supervisor-level extension for the machine mode + to enable privilege mode filtering for cycle and instret counters. + The Ssccfg extension depends on this as *cfg CSRs are available only + if smcntrpmf is present. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as