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Tue, 14 Jan 2025 14:58:48 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f10df7asm71746105ad.47.2025.01.14.14.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 14:58:47 -0800 (PST) From: Atish Patra Date: Tue, 14 Jan 2025 14:57:42 -0800 Subject: [PATCH v2 17/21] RISC-V: perf: Add legacy event encodings via sysfs Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250114-counter_delegation-v2-17-8ba74cdb851b@rivosinc.com> References: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> In-Reply-To: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 8c5e2474fb7d..8c5598253af0 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -122,7 +122,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_group = { .attrs = riscv_cdeleg_pmu_formats_attr, }; +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=" RVPMU_EVENT_ATTR_RESOLVE(mask) "\n") + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init = { + .name = "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] = { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -362,11 +375,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, \ + _cache_event_map, _attrs) \ { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ - .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ + .attrs_events = _attrs }, static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { }; @@ -388,6 +404,8 @@ static void rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid == arch_id) { current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + riscv_cdeleg_pmu_event_group.attrs = + pmu_vendor_events_table[i].attrs_events; break; } }