| Message ID | 20250205-counter_delegation-v4-7-835cfa88e3b1@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Counter delegation ISA extension support | expand |
On Wed, 05 Feb 2025 23:23:12 -0800, Atish Patra wrote: > Add the description for Smcntrpmf ISA extension > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 42e2494b126d..be9ebe927a64 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -136,6 +136,12 @@ properties: mechanism in M-mode as ratified in the 20240326 version of the privileged ISA specification. + - const: smcntrpmf + description: | + The standard Smcntrpmf supervisor-level extension for the machine mode + to enable privilege mode filtering for cycle and instret counters as + ratified in the 20240326 version of the privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as
Add the description for Smcntrpmf ISA extension Signed-off-by: Atish Patra <atishp@rivosinc.com> --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+)