From patchwork Tue Feb 18 02:15:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Longfang Liu X-Patchwork-Id: 13978838 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80ED29D05; Tue, 18 Feb 2025 02:16:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739844968; cv=none; b=R1gYsbco+3wUbTNm9h2OOpVQoa2u0S2kePqilN2cGWuCk3jJhFcFIOuIecXudx/JQSkTsqtpvRmX04xwsJuenIc2COkIr3jDBK4n5T2+08/YO7WxrAvV5TESCdzGoxlnmUPoBWxAyMCpQJkRqJdFPqPCqaG9Nl3O8tfG42cr5T8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739844968; c=relaxed/simple; bh=4CxA/zJHuoD2n5KPSk0Di2+JkzELmKBOAAPRmkLZEGk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gr2D4TkgVZikNR7X2ckbpNyJmG0FVZqJ7HAUg2r4JbLeVWAcBfD1Eh3PTbP667eOiCgUR6+32mzxQ2WDh66fXYQB5g4VUNaCK6sysE8mYPGCoE+bcJdMZ+CK0z4Czr8u6Fz6dt8a1RGxzZ1qIzIMW2eU9H+ZEAgp1dnQ+Kbp2Rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Yxjl74pwBzMqtH; Tue, 18 Feb 2025 10:14:27 +0800 (CST) Received: from kwepemg500006.china.huawei.com (unknown [7.202.181.43]) by mail.maildlp.com (Postfix) with ESMTPS id D34EC1A0188; Tue, 18 Feb 2025 10:15:56 +0800 (CST) Received: from huawei.com (10.50.165.33) by kwepemg500006.china.huawei.com (7.202.181.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 18 Feb 2025 10:15:56 +0800 From: Longfang Liu To: , , , CC: , , , Subject: [PATCH 2/3] migration: qm updates BAR configuration Date: Tue, 18 Feb 2025 10:15:06 +0800 Message-ID: <20250218021507.40740-3-liulongfang@huawei.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20250218021507.40740-1-liulongfang@huawei.com> References: <20250218021507.40740-1-liulongfang@huawei.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemg500006.china.huawei.com (7.202.181.43) On the new hardware platform, the configuration region for the live migration function of the accelerator device is no longer placed in the VF, but is instead placed in the PF. Therefore, the configuration region of the live migration function needs to be opened when the QM driver is loaded. When the QM driver is uninstalled, the driver needs to clear this configuration. Signed-off-by: Longfang Liu --- drivers/crypto/hisilicon/qm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 19c1b5d3c954..75e2e77a8f5b 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -235,6 +235,8 @@ #define QM_AUTOSUSPEND_DELAY 3000 #define QM_DEV_ALG_MAX_LEN 256 +#define QM_MIG_REGION_SEL 0x100198 +#define QM_MIG_REGION_EN 0x1 /* abnormal status value for stopping queue */ #define QM_STOP_QUEUE_FAIL 1 @@ -2895,11 +2897,36 @@ static void qm_put_pci_res(struct hisi_qm *qm) pci_release_mem_regions(pdev); } +static void hisi_mig_region_clear(struct hisi_qm *qm) +{ + u32 val; + + /* Clear migration region set of PF */ + if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) { + val = readl(qm->io_base + QM_MIG_REGION_SEL); + val &= ~BIT(0); + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + +static void hisi_mig_region_enable(struct hisi_qm *qm) +{ + u32 val; + + /* Select migration region of PF */ + if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) { + val = readl(qm->io_base + QM_MIG_REGION_SEL); + val |= QM_MIG_REGION_EN; + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + static void hisi_qm_pci_uninit(struct hisi_qm *qm) { struct pci_dev *pdev = qm->pdev; pci_free_irq_vectors(pdev); + hisi_mig_region_clear(qm); qm_put_pci_res(qm); pci_disable_device(pdev); } @@ -5497,6 +5524,7 @@ int hisi_qm_init(struct hisi_qm *qm) goto err_free_qm_memory; qm_cmd_init(qm); + hisi_mig_region_enable(qm); return 0;