Message ID | 20250327-counter_delegation-v5-20-1ee538468d1b@rivosinc.com (mailing list archive) |
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Thu, 27 Mar 2025 12:36:44 -0700 (PDT) From: Atish Patra <atishp@rivosinc.com> Date: Thu, 27 Mar 2025 12:36:01 -0700 Subject: [PATCH v5 20/21] tools/perf: Pass the Counter constraint values in the pmu events Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: <kvm.vger.kernel.org> List-Subscribe: <mailto:kvm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:kvm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250327-counter_delegation-v5-20-1ee538468d1b@rivosinc.com> References: <20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> In-Reply-To: <20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Namhyung Kim <namhyung@kernel.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>, Adrian Hunter <adrian.hunter@intel.com>, weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra <atishp@rivosinc.com> X-Mailer: b4 0.15-dev-42535 |
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Add Counter delegation ISA extension support
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expand
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diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index fdb7ddf093d2..f9f274678a32 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -274,6 +274,11 @@ class JsonEvent: return fixed[name.lower()] return event + def counter_list_to_bitmask(counterlist): + counter_ids = list(map(int, counterlist.split(','))) + bitmask = sum(1 << pos for pos in counter_ids) + return bitmask + def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" if not unit or unit == "core": @@ -427,6 +432,10 @@ class JsonEvent: else: raise argparse.ArgumentTypeError('Cannot find arch std event:', arch_std) + if self.counters['list']: + bitmask = counter_list_to_bitmask(self.counters['list']) + event += f',counterid_mask={bitmask:#x}' + self.event = real_event(self.name, event) def __repr__(self) -> str:
RISC-V doesn't have any standard event to counter mapping discovery mechanism in the ISA. The ISA defines 29 programmable counters and platforms can choose to implement any number of them and map any events to any counters. Thus, the perf tool need to inform the driver about the counter mapping of each events. The current perf infrastructure only parses the 'Counter' constraints in metrics. This patch extends that to pass in the pmu events so that any driver can retrieve those values via perf attributes if defined accordingly. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- tools/perf/pmu-events/jevents.py | 9 +++++++++ 1 file changed, 9 insertions(+)