From patchwork Sun Oct 30 06:22:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13024928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48511FA3742 for ; Sun, 30 Oct 2022 06:26:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbiJ3G0K (ORCPT ); Sun, 30 Oct 2022 02:26:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230056AbiJ3GY7 (ORCPT ); Sun, 30 Oct 2022 02:24:59 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F6F11D4; Sat, 29 Oct 2022 23:24:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667111053; x=1698647053; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uDvd5aLwQcJPBBxAxWbJDQm02RoATEZ6Bg3FqxNLsrI=; b=UaqGt3yasWfCMwcxtunmOtau4fwckFAoJF4N1ZzztxFPA8WcWhL9VRiu O7OBmXiolbYxZVH4rBq63JMYS9tTcxks89eRaO/q13Eo7RfZvT9oXrx8A XFVQPk8+KrFh+gYPtZ1NQxJIJ+RM6AS3v9jcR+u//yXrL58Tw2eLPdwia gsVdAMFZwOa8Iv6oEYVWSrMWEGWGVIjtokteNXVeh2Njl4sllGTCS6QRe wZRGYBoGPNP25bjE3SfBPdXM49TLffUwvJgrpyTEFpD0JD5fxF18KQCNt eaSwL68/IJN9ZbmZRWZ5ja/a8JHv5h8QTv98ATAe/YgP81bkvGE3SLQEb w==; X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="395037167" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="395037167" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:06 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="878393021" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="878393021" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:06 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Sean Christopherson Subject: [PATCH v10 054/108] KVM: VMX: Move setting of EPT MMU masks to common VT-x code Date: Sat, 29 Oct 2022 23:22:55 -0700 Message-Id: <251f22af488caa17dcdbb0227e7fd0b7f61f3f54.1667110240.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sean Christopherson EPT MMU masks are used commonly for VMX and TDX. The value needs to be initialized in common code before both VMX/TDX-specific initialization code. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/main.c | 5 +++++ arch/x86/kvm/vmx/vmx.c | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 0d5ca65e9997..9fb6eb626a9a 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -4,6 +4,7 @@ #include "x86_ops.h" #include "vmx.h" #include "nested.h" +#include "mmu.h" #include "pmu.h" #include "tdx.h" @@ -26,6 +27,10 @@ static __init int vt_hardware_setup(void) enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops); + if (enable_ept) + kvm_mmu_set_ept_masks(enable_ept_ad_bits, + cpu_has_vmx_ept_execute_only()); + return 0; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 2ff7af959e30..b5c3652c3cc4 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8256,10 +8256,6 @@ __init int vmx_hardware_setup(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - if (enable_ept) - kvm_mmu_set_ept_masks(enable_ept_ad_bits, - cpu_has_vmx_ept_execute_only()); - /* * Setup shadow_me_value/shadow_me_mask to include MKTME KeyID * bits to shadow_zero_check.