diff mbox series

[v2,2/7] hyperv: SVM enlightened TLB flush support flag

Message ID 3fd0cdfb9a4164a3fb90351db4dc10f52a7c4819.1618492553.git.viremana@linux.microsoft.com (mailing list archive)
State New
Headers show
Series Hyper-V nested virt enlightenments for SVM | expand

Commit Message

Vineeth Pillai April 15, 2021, 1:43 p.m. UTC
Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies
support for enlightened TLB flush. With this enlightenment enabled,
ASID invalidations flushes only gva->hpa entries. To flush TLB entries
derived from NPT, hypercalls should be used
(HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList)

Signed-off-by: Vineeth Pillai <viremana@linux.microsoft.com>
---
 arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Wei Liu April 21, 2021, 10 a.m. UTC | #1
On Thu, Apr 15, 2021 at 01:43:37PM +0000, Vineeth Pillai wrote:
> Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies
> support for enlightened TLB flush. With this enlightenment enabled,
> ASID invalidations flushes only gva->hpa entries. To flush TLB entries
> derived from NPT, hypercalls should be used
> (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList)
> 
> Signed-off-by: Vineeth Pillai <viremana@linux.microsoft.com>
> ---
>  arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
> index 606f5cc579b2..005bf14d0449 100644
> --- a/arch/x86/include/asm/hyperv-tlfs.h
> +++ b/arch/x86/include/asm/hyperv-tlfs.h
> @@ -133,6 +133,15 @@
>  #define HV_X64_NESTED_GUEST_MAPPING_FLUSH		BIT(18)
>  #define HV_X64_NESTED_MSR_BITMAP			BIT(19)
>  
> +/*
> + * This is specific to AMD and specifies that enlightened TLB flush is
> + * supported. If guest opts in to this feature, ASID invalidations only
> + * flushes gva -> hpa mapping entries. To flush the TLB entries derived
> + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
> + * or HvFlushGuestPhysicalAddressList).
> + */
> +#define HV_X64_NESTED_ENLIGHTENED_TLB			BIT(22)
> +

This is not yet documented in TLFS, right? I can't find this bit in the
latest edition (6.0b).

My first thought is the comment says this is AMD specific but the name
is rather generic. That looks a bit odd to begin with.

Wei.

>  /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
>  #define HV_PARAVISOR_PRESENT				BIT(0)
>  
> -- 
> 2.25.1
>
Vineeth Pillai April 21, 2021, 11:15 a.m. UTC | #2
On 4/21/21 6:00 AM, Wei Liu wrote:
> On Thu, Apr 15, 2021 at 01:43:37PM +0000, Vineeth Pillai wrote:
>>   
>> +/*
>> + * This is specific to AMD and specifies that enlightened TLB flush is
>> + * supported. If guest opts in to this feature, ASID invalidations only
>> + * flushes gva -> hpa mapping entries. To flush the TLB entries derived
>> + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
>> + * or HvFlushGuestPhysicalAddressList).
>> + */
>> +#define HV_X64_NESTED_ENLIGHTENED_TLB			BIT(22)
>> +
> c
> This is not yet documented in TLFS, right? I can't find this bit in the
> latest edition (6.0b).
This would be documented in the TLFS update which is soon to be
released.

>
> My first thought is the comment says this is AMD specific but the name
> is rather generic. That looks a bit odd to begin with.
I thought of of keeping the name generic to avoid renaming Intel
specific ones also. If I understand correctly, the TLFS would also
be having generic name for this and just translated the generic
name here in this header.

Thanks,
Vineeth
Wei Liu April 21, 2021, 1:20 p.m. UTC | #3
On Wed, Apr 21, 2021 at 07:15:54AM -0400, Vineeth Pillai wrote:
> 
> 
> On 4/21/21 6:00 AM, Wei Liu wrote:
> > On Thu, Apr 15, 2021 at 01:43:37PM +0000, Vineeth Pillai wrote:
> > > +/*
> > > + * This is specific to AMD and specifies that enlightened TLB flush is
> > > + * supported. If guest opts in to this feature, ASID invalidations only
> > > + * flushes gva -> hpa mapping entries. To flush the TLB entries derived
> > > + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
> > > + * or HvFlushGuestPhysicalAddressList).
> > > + */
> > > +#define HV_X64_NESTED_ENLIGHTENED_TLB			BIT(22)
> > > +
> > c
> > This is not yet documented in TLFS, right? I can't find this bit in the
> > latest edition (6.0b).
> This would be documented in the TLFS update which is soon to be
> released.

Okay.

> 
> > 
> > My first thought is the comment says this is AMD specific but the name
> > is rather generic. That looks a bit odd to begin with.
> I thought of of keeping the name generic to avoid renaming Intel
> specific ones also. If I understand correctly, the TLFS would also
> be having generic name for this and just translated the generic
> name here in this header.

Okay. Let's match what is written in TLFS.

Wei.

> 
> Thanks,
> Vineeth
>
diff mbox series

Patch

diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
index 606f5cc579b2..005bf14d0449 100644
--- a/arch/x86/include/asm/hyperv-tlfs.h
+++ b/arch/x86/include/asm/hyperv-tlfs.h
@@ -133,6 +133,15 @@ 
 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH		BIT(18)
 #define HV_X64_NESTED_MSR_BITMAP			BIT(19)
 
+/*
+ * This is specific to AMD and specifies that enlightened TLB flush is
+ * supported. If guest opts in to this feature, ASID invalidations only
+ * flushes gva -> hpa mapping entries. To flush the TLB entries derived
+ * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
+ * or HvFlushGuestPhysicalAddressList).
+ */
+#define HV_X64_NESTED_ENLIGHTENED_TLB			BIT(22)
+
 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
 #define HV_PARAVISOR_PRESENT				BIT(0)