From patchwork Mon Jan 22 09:58:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13525051 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F6DD3A8DF; Mon, 22 Jan 2024 09:47:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916840; cv=none; b=idE7V28NUReijziUCRgqpNjpQ9yCyLDwJjras5v3ByCo33fRalVngcrssOL8EjbptUNAfB/eEzZGvyOGim73XGIpyCoNcHH559g2HUnnZxeuQ2wXjwaFsZ35ZLzhkQVDni9cKBTdM0RrKtQALMj6xmKxVe/VVIRmtZpcDynFBqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916840; c=relaxed/simple; bh=bCbMxYqsNc6ysevtODH1LdEzA9cmGSP1KVajSHQPjJU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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b=FNTdXCgFDEajK0J+b4+fNPpxe5+s51uH2XqYPM3n/4RxGn1+ABwZgHvI qacCUMnlG1uDyHcLeKUCYQXBp7q7pZu/56jljYDSlvXu7sOkII9gXkEDf AzWhg0NOWbu1wYFMu4E3/ojdcSTMnSz1Ryuvh2PPh2/DnLmeUxT2XJJLT jbtuDrmtvou523Zo+2jCXrBBVmSNLiIm8Xc6P3MkHEeoOVjXVb3SH88mt jgiuwt3yiJ6dyeqoRnmWM0syD1C0fd0/fzuyETd6LQxCw3VVuIaD2qCuH 8pP87cw7w58JaImtMXQUBLL4SYKGI3gfKSr3STeVnFOSIALbwGPR6JoGK A==; X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="22641905" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="22641905" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:47:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="778535499" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="778535499" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:47:09 -0800 From: Haibo Xu To: Cc: xiaobo55x@gmail.com, ajones@ventanamicro.com, Haibo Xu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Mayuresh Chitale , Greentime Hu , wchen , Conor Dooley , Samuel Holland , Minda Chen , Jisheng Zhang , Sean Christopherson , Like Xu , Peter Xu , Vipin Sharma , Aaron Lewis , Thomas Huth , Maciej Wieczor-Retman , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v5 08/12] KVM: riscv: selftests: Switch to use macro from csr.h Date: Mon, 22 Jan 2024 17:58:38 +0800 Message-Id: <4806503d3e8fe4b727eb6df72c8fdd087355495b.1705916069.git.haibo1.xu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 5b62a3d2aa9b..6f9e1e5e466d 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -7,8 +7,9 @@ #ifndef SELFTEST_KVM_PROCESSOR_H #define SELFTEST_KVM_PROCESSOR_H -#include "kvm_util.h" #include +#include +#include "kvm_util.h" static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, uint64_t size) @@ -95,13 +96,6 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE_48 _AC(0x9000000000000000, UL) -#define SATP_ASID_BITS 16 -#define SATP_ASID_SHIFT 44 -#define SATP_ASID_MASK _AC(0xFFFF, UL) - #define SBI_EXT_EXPERIMENTAL_START 0x08000000 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF