From patchwork Thu Jul 8 00:54:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 12364249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6852BC11F7D for ; Thu, 8 Jul 2021 00:56:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50E3361452 for ; Thu, 8 Jul 2021 00:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbhGHA64 (ORCPT ); Wed, 7 Jul 2021 20:58:56 -0400 Received: from mga03.intel.com ([134.134.136.65]:19088 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230234AbhGHA6j (ORCPT ); Wed, 7 Jul 2021 20:58:39 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209462007" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209462007" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770079" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Cc: kvm@vger.kernel.org, isaku.yamahata@gmail.com, isaku.yamahata@intel.com, Sean Christopherson Subject: [RFC PATCH v2 28/44] i386/tdx: Force x2apic mode and routing for TDs Date: Wed, 7 Jul 2021 17:54:58 -0700 Message-Id: <5524acbf0b403fea046978456129d4c59a06f8a0.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sean Christopherson TDX requires x2apic and "resets" vCPUs to have x2apic enabled. Model this in QEMU and unconditionally enable x2apic interrupt routing. This fixes issues where interrupts from IRQFD would not get forwarded to the guest due to KVM silently dropping the invalid routing entry. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/intc/apic_common.c | 12 ++++++++++++ include/hw/i386/apic.h | 1 + include/hw/i386/apic_internal.h | 1 + target/i386/kvm/tdx.c | 7 +++++++ 4 files changed, 21 insertions(+) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 2a20982066..b95fed95da 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -262,6 +262,15 @@ void apic_designate_bsp(DeviceState *dev, bool bsp) } } +void apic_force_x2apic(DeviceState *dev) +{ + if (dev == NULL) { + return; + } + + APIC_COMMON(dev)->force_x2apic = true; +} + static void apic_reset_common(DeviceState *dev) { APICCommonState *s = APIC_COMMON(dev); @@ -270,6 +279,9 @@ static void apic_reset_common(DeviceState *dev) bsp = s->apicbase & MSR_IA32_APICBASE_BSP; s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; + if (s->force_x2apic) { + s->apicbase |= MSR_IA32_APICBASE_EXTD; + } s->id = s->initial_apic_id; apic_reset_irq_delivered(); diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index da1d2fe155..7d05abd7e0 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -19,6 +19,7 @@ void apic_init_reset(DeviceState *s); void apic_sipi(DeviceState *s); void apic_poll_irq(DeviceState *d); void apic_designate_bsp(DeviceState *d, bool bsp); +void apic_force_x2apic(DeviceState *d); int apic_get_highest_priority_irr(DeviceState *dev); /* pc.c */ diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index c175e7e718..eda0b5a587 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -187,6 +187,7 @@ struct APICCommonState { DeviceState *vapic; hwaddr vapic_paddr; /* note: persistence via kvmvapic */ bool legacy_instance_id; + bool force_x2apic; }; typedef struct VAPICState { diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index c348626dbf..47a502051c 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -139,6 +139,11 @@ int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) tdx_caps->nr_cpuid_configs = TDX1_MAX_NR_CPUID_CONFIGS; tdx_ioctl(KVM_TDX_CAPABILITIES, 0, tdx_caps); + if (!kvm_enable_x2apic()) { + error_report("Failed to enable x2apic in KVM"); + exit(1); + } + qemu_add_machine_init_done_late_notifier(&tdx_machine_done_late_notify); return 0; @@ -296,6 +301,8 @@ void tdx_post_init_vcpu(CPUState *cpu) hob = tdx_get_hob_entry(tdx); _tdx_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, (void *)hob->address); + + apic_force_x2apic(X86_CPU(cpu)->apic_state); } static bool tdx_guest_get_debug(Object *obj, Error **errp)