From patchwork Mon Jan 22 23:54:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13526508 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79C2B679F5; Mon, 22 Jan 2024 23:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.55.52.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967758; cv=none; b=gxRUIG2X78Z5J3ZT0DsJ+Nbx5uJFn5IjgFGypYnzyp5n0NmhUJxPvkXEtHStr7IkTgxXBeTYXPISLLRfWPS9bN/wjp07y7kp8IuRDySTxxhHaJ8yquU3Im7PBYliDD2+0/iMNFne2qouSgmmlwki6/JxfuvmX8d+Ep57pRnCQZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967758; c=relaxed/simple; bh=YHCPMO+jdibw4QTTP7e8hAPdsySz1/Jza7ODNI+BEMs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jxmW7kRY/9PmhRnDpZGLyRpQ0MeGCqLUqUndRWFxutqV9JAjXZuIdAfBbJAnMCye6Yn6cvPf7vjyb/Yq4xEmlqGNU1rNUQA/neHECwWfohjTyc0nqId1sAXyDU0frVuiWNmfXtBfSyHwJe6U7VVUu1u5+zfYuzMKLNdM3QuFTs8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Bx3+pIvf; arc=none smtp.client-ip=192.55.52.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Bx3+pIvf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705967756; x=1737503756; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YHCPMO+jdibw4QTTP7e8hAPdsySz1/Jza7ODNI+BEMs=; b=Bx3+pIvf///ghJlKW0u/UjF6prtEkUUkRuYZ96a6XkR5gsnVrlz3xzaP 5wRlCSa7zoYvn/LZRRVWE8OqeBiiIbKKjKOFVyy6bxjujmQIxHQtC6yzU NVx28YUGCyifuHrJQo3TlVuRf0sBGYeGzUCk8wQCP/Lso1wm14wM1xaB9 +YMtV7KwGq1tC8YhauRW3c8dnSc0jPIP0NTtz4N52vBMcYp5+OFao7DJs LQixkoLnzGn4dkSeX16tmY+bdDxNpy+akhCXosUmdsjI27x9PpqEOJtJr Gm+UHovgrMdCeKP3TV2mA5K071ri16g/LwBsIjqJedBpDvnuqBoPh5g7/ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="400217830" X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="400217830" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="27817951" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:48 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v18 090/121] KVM: TDX: handle ept violation/misconfig exit Date: Mon, 22 Jan 2024 15:54:06 -0800 Message-Id: <62a4a92cf2c0d112de775129d0a592459fe778d1.1705965635.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Isaku Yamahata On EPT violation, call a common function, __vmx_handle_ept_violation() to trigger x86 MMU code. On EPT misconfiguration, exit to ring 3 with KVM_EXIT_UNKNOWN. because EPT misconfiguration can't happen as MMIO is trigged by TDG.VP.VMCALL. No point to set a misconfiguration value for the fast path. Signed-off-by: Isaku Yamahata --- v14 -> v15: - use PFERR_GUEST_ENC_MASK to tell the fault is private --- arch/x86/kvm/vmx/common.h | 3 +++ arch/x86/kvm/vmx/tdx.c | 49 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/x86/kvm/vmx/common.h b/arch/x86/kvm/vmx/common.h index 632af7a76d0a..027aa4175d2c 100644 --- a/arch/x86/kvm/vmx/common.h +++ b/arch/x86/kvm/vmx/common.h @@ -87,6 +87,9 @@ static inline int __vmx_handle_ept_violation(struct kvm_vcpu *vcpu, gpa_t gpa, error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ? PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; + if (kvm_is_private_gpa(vcpu->kvm, gpa)) + error_code |= PFERR_GUEST_ENC_MASK; + return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); } diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 96f43ce288c3..4418f04a1cf1 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1330,6 +1330,51 @@ void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, __vmx_deliver_posted_interrupt(vcpu, &tdx->pi_desc, vector); } +static int tdx_handle_ept_violation(struct kvm_vcpu *vcpu) +{ + unsigned long exit_qual; + + if (kvm_is_private_gpa(vcpu->kvm, tdexit_gpa(vcpu))) { + /* + * Always treat SEPT violations as write faults. Ignore the + * EXIT_QUALIFICATION reported by TDX-SEAM for SEPT violations. + * TD private pages are always RWX in the SEPT tables, + * i.e. they're always mapped writable. Just as importantly, + * treating SEPT violations as write faults is necessary to + * avoid COW allocations, which will cause TDAUGPAGE failures + * due to aliasing a single HPA to multiple GPAs. + */ +#define TDX_SEPT_VIOLATION_EXIT_QUAL EPT_VIOLATION_ACC_WRITE + exit_qual = TDX_SEPT_VIOLATION_EXIT_QUAL; + } else { + exit_qual = tdexit_exit_qual(vcpu); + if (exit_qual & EPT_VIOLATION_ACC_INSTR) { + pr_warn("kvm: TDX instr fetch to shared GPA = 0x%lx @ RIP = 0x%lx\n", + tdexit_gpa(vcpu), kvm_rip_read(vcpu)); + vcpu->run->exit_reason = KVM_EXIT_EXCEPTION; + vcpu->run->ex.exception = PF_VECTOR; + vcpu->run->ex.error_code = exit_qual; + return 0; + } + } + + trace_kvm_page_fault(vcpu, tdexit_gpa(vcpu), exit_qual); + return __vmx_handle_ept_violation(vcpu, tdexit_gpa(vcpu), exit_qual); +} + +static int tdx_handle_ept_misconfig(struct kvm_vcpu *vcpu) +{ + WARN_ON_ONCE(1); + + vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; + vcpu->run->internal.ndata = 2; + vcpu->run->internal.data[0] = EXIT_REASON_EPT_MISCONFIG; + vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu; + + return 0; +} + int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) { union tdx_exit_reason exit_reason = to_tdx(vcpu)->exit_reason; @@ -1390,6 +1435,10 @@ int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) WARN_ON_ONCE(fastpath != EXIT_FASTPATH_NONE); switch (exit_reason.basic) { + case EXIT_REASON_EPT_VIOLATION: + return tdx_handle_ept_violation(vcpu); + case EXIT_REASON_EPT_MISCONFIG: + return tdx_handle_ept_misconfig(vcpu); case EXIT_REASON_OTHER_SMI: /* * If reach here, it's not a Machine Check System Management