From patchwork Mon Jan 22 23:54:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13526516 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C06BF6A346; Mon, 22 Jan 2024 23:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.55.52.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967761; cv=none; b=RMTnwZ4Baj/mPq1QKXyBUO7fUJ6dEuCQNRdW/QPotP7wb5kV7nmNkTEX9bosGhJuRnKUKeb0bicuMOHeGy7K4GMSbMabQcdXbgdKU1MUGdKBzgqkR6jaEc7t9vbcdaRoMaZeR5SPrL5tGHrVGLbUw6omEqkkrxV26rbqFpI14sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967761; c=relaxed/simple; bh=wGtXGF0lMiZWLOH+oSNj/3dY7kZ4QLS7boBDRkmZahg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SlN4b2s1h/fhZ3Z4nFm8nAAjqt09pSpOx0nlAZzUF/Zt1S4YB70epR+85YQVyIbO8JfB+MnajT8tw3UAjCSuDvgtFbiNtLOhVKiRSUhkgR5OzITBMFzH6h264zCPDHsgchZZJOM8wwoekE0w1UkNXLA2Em7G0zolE7rvRWggz1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IAoDxlH2; arc=none smtp.client-ip=192.55.52.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IAoDxlH2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705967759; x=1737503759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wGtXGF0lMiZWLOH+oSNj/3dY7kZ4QLS7boBDRkmZahg=; b=IAoDxlH2h0NzxRgYCsRBCmUjUccoRngMX6RpZdxoCe7/6TQcgwg/Da2t JENKsLQsahMrj9fi7kDP0IewyUZPI7zPPwxu9z+dKAt953SXZJENRyQzM u4IwrloNp7NKQ1ifsJnvPUafdlZO4kBzgM5zXD5IR6EoQWi0BWG+XX/hd YWPZxXO/m0q8XrAOhfTunBYYktNSw4pmc92zGjuj89DkMBpJOVW/jZAwl QYbyAcLZKU74fHW1uJD66jTkFrqMe2kvWhnSK5NplHXncjeJCOlc2VeGk BcwsC9vSaErW7/95Rege/tWe93gTw2phmp1SSfRWCruxiTEEvQAgKjPL+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="400217854" X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="400217854" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="27817974" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:50 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v18 096/121] KVM: TDX: Handle TDX PV CPUID hypercall Date: Mon, 22 Jan 2024 15:54:12 -0800 Message-Id: <63097ba137cf2cf08425d8ac1655e19bfe2b52d0.1705965635.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Isaku Yamahata Wire up TDX PV CPUID hypercall to the KVM backend function. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/tdx.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index c504c5d9debf..f952a95e493d 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1160,12 +1160,34 @@ static int tdx_vp_vmcall_to_user(struct kvm_vcpu *vcpu) return 0; } +static int tdx_emulate_cpuid(struct kvm_vcpu *vcpu) +{ + u32 eax, ebx, ecx, edx; + + /* EAX and ECX for cpuid is stored in R12 and R13. */ + eax = tdvmcall_a0_read(vcpu); + ecx = tdvmcall_a1_read(vcpu); + + kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); + + tdvmcall_a0_write(vcpu, eax); + tdvmcall_a1_write(vcpu, ebx); + tdvmcall_a2_write(vcpu, ecx); + tdvmcall_a3_write(vcpu, edx); + + tdvmcall_set_return_code(vcpu, TDG_VP_VMCALL_SUCCESS); + + return 1; +} + static int handle_tdvmcall(struct kvm_vcpu *vcpu) { if (tdvmcall_exit_type(vcpu)) return tdx_emulate_vmcall(vcpu); switch (tdvmcall_leaf(vcpu)) { + case EXIT_REASON_CPUID: + return tdx_emulate_cpuid(vcpu); default: break; }