From patchwork Mon Jan 22 09:58:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13525081 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 304AA3B790; Mon, 22 Jan 2024 09:48:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916892; cv=none; b=RXIKjsHNCN/f4Be8cIScPwF/eC/Qxq7K2kEGCWROt/BZFQkLInnoKpKp/u6HwQqsEatB1oevicZcFrmIETEk9b/fKijyKcnQjQigss6JayVa6r6KGIrb2Zv4e684DVCUrjsOXy/mLKfG8980v8HH4ijRVP8KXW6ZWrzhrHOnU7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916892; c=relaxed/simple; bh=2adDNSs11ffydm0AYsw6Seh3zPpXT0ndS2F8Q7hAt1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p+Ni6hQ2Mt7ZKAiQ4lRIgX7BU5Nrb5fmZSIv1FF8uMvcExrn9KTYcG6XKHWVfH8YxU7bUw35P4pMlFDER3xmNMcXYJjMponKC4HAyY8rCn3JAfBIObxgsZs2qiI3737TFQ7earpl/b/HpbjcgarbAgHxBYncJlDru14Nid+n66A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=b8bypusW; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="b8bypusW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705916891; x=1737452891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2adDNSs11ffydm0AYsw6Seh3zPpXT0ndS2F8Q7hAt1Q=; b=b8bypusWCG2CK21aj+ju8IMswbpLzD4qa+5Zrx8JiAB+f2ZQ9BHzW4zn te3Fe8zkieUrIRaa4P0Uka1xlEw2R24bgRAabk+7IUVuPBEb4xwDv90PZ 51e472tJS+rG/ZmEYS2dT7e1b0jJ1Y8uS2dZ+/+fFNNJIsnlg7xluHnHz fv0t16yXVLzNL5VkrH5vGvb2UsSLC6G4ttj89OVyZ3/gtPPx2Qgg7cMX3 a7+5VStGmgoFH3KS+rAAugUfyHX4uuBVTt6o2SteAINIPof7iK8mohMef yf2ji6Q9wBIiXI6iN9uFc8Y1xmmedBwPfyrGsBz0EP8tX3er1pbspMhz1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="22642040" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="22642040" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:48:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="778535584" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="778535584" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:48:00 -0800 From: Haibo Xu To: Cc: xiaobo55x@gmail.com, ajones@ventanamicro.com, Haibo Xu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Mayuresh Chitale , Daniel Henrique Barboza , Conor Dooley , Samuel Holland , Minda Chen , Jisheng Zhang , Sean Christopherson , Peter Xu , Like Xu , Vipin Sharma , Thomas Huth , Aaron Lewis , Maciej Wieczor-Retman , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v5 11/12] KVM: riscv: selftests: Change vcpu_has_ext to a common function Date: Mon, 22 Jan 2024 17:58:41 +0800 Message-Id: <68856b86a93a4188558e5d0ebac0dd6aac8e404c.1705916069.git.haibo1.xu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext so that other test cases can use it for vCPU extension check. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 2 ++ tools/testing/selftests/kvm/lib/riscv/processor.c | 10 ++++++++++ tools/testing/selftests/kvm/riscv/get-reg-list.c | 11 +---------- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index b68b1b731a34..bd27e1c67579 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -42,6 +42,8 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, #define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ idx, KVM_REG_SIZE_ULONG) +bool __vcpu_has_ext(struct kvm_vcpu *vcpu, int ext); + struct ex_regs { unsigned long ra; unsigned long sp; diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index 39a1e9902dec..dad73ce18164 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -15,6 +15,16 @@ static vm_vaddr_t exception_handlers; +bool __vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) +{ + unsigned long value = 0; + int ret; + + ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value); + + return !ret && !!value; +} + static uint64_t page_align(struct kvm_vm *vm, uint64_t v) { return (v + vm->page_size) & ~(vm->page_size - 1); diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 25de4b8bc347..ed29ba45588c 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -75,15 +75,6 @@ bool check_reject_set(int err) return err == EINVAL; } -static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) -{ - int ret; - unsigned long value; - - ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value); - return (ret) ? false : !!value; -} - void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; @@ -111,7 +102,7 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(s->feature), 1); /* Double check whether the desired extension was enabled */ - __TEST_REQUIRE(vcpu_has_ext(vcpu, s->feature), + __TEST_REQUIRE(__vcpu_has_ext(vcpu, s->feature), "%s not available, skipping tests\n", s->name); } }